tellpw.tan.rpt

来自「一些很好的FPGA设计实例」· RPT 代码 · 共 592 行 · 第 1/4 页

; N/A           ; None        ; -10.000 ns ; DIN[10]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.000 ns ; DIN[10]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[5]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[3]   ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[3]   ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[23]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[23]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DATA[2]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DATA[2]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DATA[10] ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DIN[10]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.100 ns ; DATA[17] ; ok~reg0   ; cfm      ;
; N/A           ; None        ; -10.200 ns ; DIN[3]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.200 ns ; DIN[23]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.200 ns ; DIN[20]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.200 ns ; DIN[20]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.200 ns ; DATA[2]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DIN[20]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DATA[0]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DATA[0]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DIN[0]   ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DIN[0]   ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.300 ns ; DIN[7]   ; ok~reg0   ; cfm      ;
; N/A           ; None        ; -10.400 ns ; DATA[0]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.400 ns ; DIN[0]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.400 ns ; DIN[2]   ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.400 ns ; DIN[2]   ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.400 ns ; DATA[4]  ; ok~reg0   ; cfm      ;
; N/A           ; None        ; -10.500 ns ; DIN[2]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.600 ns ; DATA[18] ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.600 ns ; DATA[18] ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.600 ns ; DATA[15] ; ok~reg0   ; cfm      ;
; N/A           ; None        ; -10.600 ns ; DATA[22] ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.600 ns ; DATA[22] ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.700 ns ; DATA[3]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.700 ns ; DATA[3]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.700 ns ; DATA[18] ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.700 ns ; DATA[22] ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.800 ns ; DATA[3]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.800 ns ; DATA[7]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.800 ns ; DATA[7]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.900 ns ; DIN[22]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.900 ns ; DIN[22]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -10.900 ns ; DATA[7]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -10.900 ns ; DIN[17]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -10.900 ns ; DIN[17]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.000 ns ; DIN[22]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.000 ns ; DIN[17]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.100 ns ; DIN[15]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.100 ns ; DIN[15]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.200 ns ; DIN[15]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.200 ns ; DIN[4]   ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.200 ns ; DIN[4]   ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.300 ns ; DIN[4]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.400 ns ; DATA[17] ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.400 ns ; DATA[17] ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.500 ns ; DATA[17] ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.600 ns ; DIN[7]   ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.600 ns ; DIN[7]   ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.700 ns ; DATA[4]  ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.700 ns ; DATA[4]  ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -11.700 ns ; DIN[7]   ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.800 ns ; DATA[4]  ; lock~reg0 ; cfm      ;
; N/A           ; None        ; -11.900 ns ; DATA[15] ; n[0]~reg0 ; cfm      ;
; N/A           ; None        ; -11.900 ns ; DATA[15] ; n[1]~reg0 ; cfm      ;
; N/A           ; None        ; -12.000 ns ; DATA[15] ; lock~reg0 ; cfm      ;
+---------------+-------------+------------+----------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Feb 28 04:37:58 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off tellpw -c tellpw
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "cfm" is an undefined clock
Info: Clock "cfm" Internal fmax is restricted to 200.0 MHz between source register "n[1]~reg0" and destination register "n[1]~reg0"
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.900 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n[1]~reg0'
            Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 0.900 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n[1]~reg0'
            Info: Total cell delay = 0.700 ns ( 77.78 % )
            Info: Total interconnect delay = 0.200 ns ( 22.22 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "cfm" to destination register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n[1]~reg0'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
            Info: - Longest clock path from clock "cfm" to source register is 1.800 ns
                Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'
                Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC2_D8; Fanout = 3; REG Node = 'n[1]~reg0'
                Info: Total cell delay = 1.500 ns ( 83.33 % )
                Info: Total interconnect delay = 0.300 ns ( 16.67 % )
        Info: + Micro clock to output delay of source is 0.400 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "lock~reg0" (data pin = "DATA[15]", clock pin = "cfm") is 13.600 ns
    Info: + Longest pin to register delay is 14.800 ns
        Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_122; Fanout = 1; PIN Node = 'DATA[15]'
        Info: 2: + IC(2.200 ns) + CELL(0.700 ns) = 6.400 ns; Loc. = LC7_E24; Fanout = 1; COMB Node = 'Equal0~350'
        Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 7.600 ns; Loc. = LC8_E24; Fanout = 1; COMB Node = 'Equal0~331'
        Info: 4: + IC(1.500 ns) + CELL(1.100 ns) = 10.200 ns; Loc. = LC5_B25; Fanout = 2; COMB Node = 'Equal0~301'
        Info: 5: + IC(2.400 ns) + CELL(1.200 ns) = 13.800 ns; Loc. = LC6_D8; Fanout = 3; COMB Node = 'Equal0~302'
        Info: 6: + IC(0.200 ns) + CELL(0.800 ns) = 14.800 ns; Loc. = LC1_D8; Fanout = 2; REG Node = 'lock~reg0'
        Info: Total cell delay = 8.500 ns ( 57.43 % )
        Info: Total interconnect delay = 6.300 ns ( 42.57 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "cfm" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_D8; Fanout = 2; REG Node = 'lock~reg0'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
Info: tco from clock "cfm" to destination pin "ok" through register "ok~reg0" is 8.700 ns
    Info: + Longest clock path from clock "cfm" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.400 ns
    Info: + Longest register to pin delay is 6.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'
        Info: 2: + IC(1.900 ns) + CELL(4.600 ns) = 6.500 ns; Loc. = PIN_29; Fanout = 0; PIN Node = 'ok'
        Info: Total cell delay = 4.600 ns ( 70.77 % )
        Info: Total interconnect delay = 1.900 ns ( 29.23 % )
Info: th for register "ok~reg0" (data pin = "DATA[8]", clock pin = "cfm") is -0.500 ns
    Info: + Longest clock path from clock "cfm" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 4; CLK Node = 'cfm'
        Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'
        Info: Total cell delay = 1.500 ns ( 83.33 % )
        Info: Total interconnect delay = 0.300 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.000 ns
    Info: - Shortest pin to register delay is 3.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_184; Fanout = 1; PIN Node = 'DATA[8]'
        Info: 2: + IC(0.200 ns) + CELL(0.900 ns) = 2.600 ns; Loc. = LC3_D8; Fanout = 2; COMB Node = 'Equal0~294'
        Info: 3: + IC(0.200 ns) + CELL(0.500 ns) = 3.300 ns; Loc. = LC5_D8; Fanout = 1; REG Node = 'ok~reg0'
        Info: Total cell delay = 2.900 ns ( 87.88 % )
        Info: Total interconnect delay = 0.400 ns ( 12.12 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Feb 28 04:37:59 2007
    Info: Elapsed time: 00:00:01