led_display.tan.qmsg

一些很好的FPGA设计实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "7493:inst1\|16 " "Info: Detected ripple clock \"7493:inst1\|16\" as buffer" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "7493:inst1\|16" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register 7493:inst1\|14 7493:inst1\|13 200.0 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 200.0 MHz between source register \"7493:inst1\|14\" and destination register \"7493:inst1\|13\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.900 ns + Longest register register " "Info: + Longest register to register delay is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst1\|14 1 REG LC2_C7 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C7; Fanout = 19; REG Node = '7493:inst1\|14'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 1.300 ns 7493:inst1\|39 2 COMB LC1_C7 1 " "Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC1_C7; Fanout = 1; COMB Node = '7493:inst1\|39'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 7493:inst1|14 7493:inst1|39 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 464 240 304 504 "39" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.800 ns) 2.900 ns 7493:inst1\|13 3 REG LC1_C6 18 " "Info: 3: + IC(0.800 ns) + CELL(0.800 ns) = 2.900 ns; Loc. = LC1_C6; Fanout = 18; REG Node = '7493:inst1\|13'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.600 ns" { 7493:inst1|39 7493:inst1|13 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 65.52 % ) " "Info: Total cell delay = 1.900 ns ( 65.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 34.48 % ) " "Info: Total interconnect delay = 1.000 ns ( 34.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { 7493:inst1|14 7493:inst1|39 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.900 ns" { 7493:inst1|14 7493:inst1|39 7493:inst1|13 } { 0.000ns 0.200ns 0.800ns } { 0.000ns 1.100ns 0.800ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 5.400 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 488 240 408 504 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst1\|16 2 REG LC1_C8 21 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns 7493:inst1\|13 3 REG LC1_C6 18 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC1_C6; Fanout = 18; REG Node = '7493:inst1\|13'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { 7493:inst1|16 7493:inst1|13 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|13 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.400 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 488 240 408 504 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst1\|16 2 REG LC1_C8 21 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns 7493:inst1\|14 3 REG LC2_C7 19 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC2_C7; Fanout = 19; REG Node = '7493:inst1\|14'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { 7493:inst1|16 7493:inst1|14 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|14 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|14 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|13 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|14 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|14 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 320 480 544 400 "14" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { 7493:inst1|14 7493:inst1|39 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.900 ns" { 7493:inst1|14 7493:inst1|39 7493:inst1|13 } { 0.000ns 0.200ns 0.800ns } { 0.000ns 1.100ns 0.800ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|13 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|14 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|14 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|13 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { 7493:inst1|13 } {  } {  } } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK q\[11\] 7493:inst1\|15 23.600 ns register " "Info: tco from clock \"CLK\" to destination pin \"q\[11\]\" through register \"7493:inst1\|15\" is 23.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 5.400 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_79 1 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_79; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 488 240 408 504 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns 7493:inst1\|16 2 REG LC1_C8 21 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_C8; Fanout = 21; REG Node = '7493:inst1\|16'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { CLK 7493:inst1|16 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 5.400 ns 7493:inst1\|15 3 REG LC5_C7 20 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 5.400 ns; Loc. = LC5_C7; Fanout = 20; REG Node = '7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 35.19 % ) " "Info: Total cell delay = 1.900 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.500 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.800 ns + Longest register pin " "Info: + Longest register to pin delay is 17.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:inst1\|15 1 REG LC5_C7 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C7; Fanout = 20; REG Node = '7493:inst1\|15'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { 7493:inst1|15 } "NODE_NAME" } } { "7493.bdf" "" { Schematic "d:/altera/quartus60/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(5.600 ns) 7.700 ns lpm_rom:inst\|altrom:srom\|q\[11\]~mem_cell_ra0 2 MEM EC7_F 1 " "Info: 2: + IC(2.100 ns) + CELL(5.600 ns) = 7.700 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[11\]~mem_cell_ra0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.700 ns" { 7493:inst1|15 lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 8.900 ns lpm_rom:inst\|altrom:srom\|q\[11\] 3 MEM EC7_F 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 8.900 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 12.500 ns q\[11\]~4 4 COMB LC1_B20 1 " "Info: 4: + IC(2.700 ns) + CELL(0.900 ns) = 12.500 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'q\[11\]~4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { lpm_rom:inst|altrom:srom|q[11] q[11]~4 } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 240 744 920 256 "q\[15..0\]" "" } { 232 696 753 248 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(4.600 ns) 17.800 ns q\[11\] 5 PIN PIN_74 0 " "Info: 5: + IC(0.700 ns) + CELL(4.600 ns) = 17.800 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { q[11]~4 q[11] } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 240 744 920 256 "q\[15..0\]" "" } { 232 696 753 248 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.300 ns ( 69.10 % ) " "Info: Total cell delay = 12.300 ns ( 69.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 30.90 % ) " "Info: Total interconnect delay = 5.500 ns ( 30.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.800 ns" { 7493:inst1|15 lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.800 ns" { 7493:inst1|15 lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } { 0.000ns 2.100ns 0.000ns 2.700ns 0.700ns } { 0.000ns 5.600ns 1.200ns 0.900ns 4.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { CLK 7493:inst1|16 7493:inst1|15 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.400 ns" { CLK CLK~out 7493:inst1|16 7493:inst1|15 } { 0.000ns 0.000ns 0.300ns 3.200ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.800 ns" { 7493:inst1|15 lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "17.800 ns" { 7493:inst1|15 lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } { 0.000ns 2.100ns 0.000ns 2.700ns 0.700ns } { 0.000ns 5.600ns 1.200ns 0.900ns 4.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "addr\[4\] q\[11\] 21.900 ns Longest " "Info: Longest tpd from source pin \"addr\[4\]\" to destination pin \"q\[11\]\" is 21.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns addr\[4\] 1 PIN PIN_53 16 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_53; Fanout = 16; PIN Node = 'addr\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { addr[4] } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 152 160 328 168 "addr\[7..4\]" "" } { 96 400 504 112 "addr\[7..4\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(5.600 ns) 11.800 ns lpm_rom:inst\|altrom:srom\|q\[11\]~mem_cell_ra0 2 MEM EC7_F 1 " "Info: 2: + IC(2.700 ns) + CELL(5.600 ns) = 11.800 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[11\]~mem_cell_ra0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.300 ns" { addr[4] lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 13.000 ns lpm_rom:inst\|altrom:srom\|q\[11\] 3 MEM EC7_F 1 " "Info: 3: + IC(0.000 ns) + CELL(1.200 ns) = 13.000 ns; Loc. = EC7_F; Fanout = 1; MEM Node = 'lpm_rom:inst\|altrom:srom\|q\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.200 ns" { lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.900 ns) 16.600 ns q\[11\]~4 4 COMB LC1_B20 1 " "Info: 4: + IC(2.700 ns) + CELL(0.900 ns) = 16.600 ns; Loc. = LC1_B20; Fanout = 1; COMB Node = 'q\[11\]~4'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { lpm_rom:inst|altrom:srom|q[11] q[11]~4 } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 240 744 920 256 "q\[15..0\]" "" } { 232 696 753 248 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(4.600 ns) 21.900 ns q\[11\] 5 PIN PIN_74 0 " "Info: 5: + IC(0.700 ns) + CELL(4.600 ns) = 21.900 ns; Loc. = PIN_74; Fanout = 0; PIN Node = 'q\[11\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.300 ns" { q[11]~4 q[11] } "NODE_NAME" } } { "LED_DISPLAY.bdf" "" { Schematic "D:/altera/ym/text10/epasswordlock/LED_DISPLAY/LED_DISPLAY.bdf" { { 240 744 920 256 "q\[15..0\]" "" } { 232 696 753 248 "q\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.800 ns ( 72.15 % ) " "Info: Total cell delay = 15.800 ns ( 72.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns ( 27.85 % ) " "Info: Total interconnect delay = 6.100 ns ( 27.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "21.900 ns" { addr[4] lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "21.900 ns" { addr[4] addr[4]~out lpm_rom:inst|altrom:srom|q[11]~mem_cell_ra0 lpm_rom:inst|altrom:srom|q[11] q[11]~4 q[11] } { 0.000ns 0.000ns 2.700ns 0.000ns 2.700ns 0.700ns } { 0.000ns 3.500ns 5.600ns 1.200ns 0.900ns 4.600ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 02 03:07:32 2007 " "Info: Processing ended: Fri Mar 02 03:07:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}