count60.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.aLL;
ENTITY count60 is
PORT(carry:in std_logic;
     rst:in std_logic;
     times:out integer range 0 to 59;
     full:out std_logic);
END count60;
ARCHITECTURE arch OF count60 IS 
     signal time :integer range 0 to 59;
BEGIN
 process (rst,carry)
 begin
   if rst='1' then time <= 0;full <= '0';
   else if rising_edge(carry)then
          if time= 59 then time<=0;
                          full<='1';
                     else time<=time+1;
                          full<='0';
          end if;
   end if;
 end process;
 times<=timne;
END arch;