adder_1.map.summary

一些很好的FPGA设计实例

Analysis & Synthesis Status : Successful - Tue Mar 20 21:24:49 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : adder_1
Top-level Entity Name : adder_1
Family : FLEX10K
Total logic elements : 2
Total pins : 5
Total memory bits : 0