vote.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 46 行

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module vote(
	in1,
	in2,
	in3,
	led1,
	led2
);

input	in1;
input	in2;
input	in3;
output	led1;
output	led2;

wire	a;
wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;




assign	SYNTHESIZED_WIRE_1 = in3 & in2;
assign	SYNTHESIZED_WIRE_2 = in1 & in3;
assign	SYNTHESIZED_WIRE_0 = in2 & in1;
assign	a = SYNTHESIZED_WIRE_0 | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
assign	led2 =  ~a;
assign	led1 = a;


endmodule