f_adder.map.summary

来自「一些很好的FPGA设计实例」· SUMMARY 代码 · 共 10 行

Analysis & Synthesis Status : Successful - Sat Mar 24 15:33:40 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : f_adder
Top-level Entity Name : f_adder
Family : ACEX1K
Total logic elements : 2
Total pins : 5
Total memory bits : 0
Total PLLs : 0