division3.tan.rpt

一些很好的FPGA设计实例

; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[3]  ; temp2[0]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[1]  ; temp2[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[0]  ; temp2[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[2]  ; temp2[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[1]  ; temp2[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[0]  ; temp2[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[2]  ; temp2[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[3]  ; temp2[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[1]  ; temp1[1]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[0]  ; temp1[1]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[2]  ; temp1[1]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[3]  ; temp1[1]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[1]  ; temp1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[0]  ; temp1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[2]  ; temp1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[3]  ; temp1[0]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[1]  ; temp1[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[0]  ; temp1[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[2]  ; temp1[2]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[1]  ; temp1[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[0]  ; temp1[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[2]  ; temp1[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[3]  ; temp1[3]  ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[1]  ; division4 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[0]  ; division4 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[2]  ; division4 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp2[3]  ; division4 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; division4 ; division4 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[1]  ; division2 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[0]  ; division2 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[2]  ; division2 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; temp1[3]  ; division2 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; division2 ; division2 ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
+-------+-----------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 13.000 ns  ; division4 ; out1 ; clk        ;
; N/A   ; None         ; 13.000 ns  ; division2 ; out1 ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Oct 01 08:44:18 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off division3 -c division3
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 100.0 MHz between source register "temp2[1]" and destination register "temp2[1]" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 8; REG Node = 'temp2[1]'
        Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC2; Fanout = 8; REG Node = 'temp2[1]'
        Info: Total cell delay = 5.000 ns ( 83.33 % )
        Info: Total interconnect delay = 1.000 ns ( 16.67 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 8; REG Node = 'temp2[1]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2; Fanout = 8; REG Node = 'temp2[1]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "clk" to destination pin "out1" through register "division4" is 13.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 10; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC10; Fanout = 4; REG Node = 'division4'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 9.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC10; Fanout = 4; REG Node = 'division4'
        Info: 2: + IC(1.000 ns) + CELL(7.000 ns) = 8.000 ns; Loc. = LC1; Fanout = 1; COMB Node = 'out1~3'
        Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 9.500 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'out1'
        Info: Total cell delay = 8.500 ns ( 89.47 % )
        Info: Total interconnect delay = 1.000 ns ( 10.53 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Oct 01 08:44:18 2008
    Info: Elapsed time: 00:00:00