odd_fren.tan.summary

一些很好的FPGA设计实例

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 18.000 ns
From           : O~reg0
To             : O
From Clock     : Clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'Clk'
Slack          : N/A
Required Time  : None
Actual Time    : 100.00 MHz ( period = 10.000 ns )
From           : O~reg0
To             : O~reg0
From Clock     : Clk
To Clock       : Clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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