clkdiv.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 38 行

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY  clkdiv  IS
         PORT(
              clk        : IN STD_LOGIC;
             clk_div2    : OUT STD_LOGIC;
             clk_div3    : OUT STD_LOGIC;
             clk_div4    : OUT STD_LOGIC;
             clk_div8    : OUT STD_LOGIC;
             clk_div16   : OUT STD_LOGIC


              );
END clkdiv;

ARCHITECTURE rtl OF clkdiv IS
      SIGNAL  count : STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
      PROCESS(clk)
      BEGIN
         IF(clk'event AND clk = '1') THEN
             IF(count="111111")THEN
              count <= (OTHERS => '0');
            ELSE
              count <= count +1;
            END IF ;
         END IF ;
  END PROCESS;
      clk_div2 <= count(0);
      clk_div4 <= count(2);
      clk_div8 <= count(4);
      clk_div16<= count(5);


END rtl;