clkdiv.tan.rpt

来自「一些很好的FPGA设计实例」· RPT 代码 · 共 169 行 · 第 1/2 页

+-------+-----------------------------------+---------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)              ; From                            ; To                              ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+-----------------------------------+---------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[0] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[1] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1] ; lpm_counter:count_rtl_0|dffs[1] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1] ; lpm_counter:count_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2] ; lpm_counter:count_rtl_0|dffs[2] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1] ; lpm_counter:count_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2] ; lpm_counter:count_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3] ; lpm_counter:count_rtl_0|dffs[3] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[4] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1] ; lpm_counter:count_rtl_0|dffs[4] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2] ; lpm_counter:count_rtl_0|dffs[4] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3] ; lpm_counter:count_rtl_0|dffs[4] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[4] ; lpm_counter:count_rtl_0|dffs[4] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[0] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[1] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[2] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[3] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[4] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
; N/A   ; 100.00 MHz ( period = 10.000 ns ) ; lpm_counter:count_rtl_0|dffs[5] ; lpm_counter:count_rtl_0|dffs[5] ; clk        ; clk      ; None                        ; None                      ; 6.000 ns                ;
+-------+-----------------------------------+---------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------------------------------+
; tco                                                                                          ;
+-------+--------------+------------+---------------------------------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From                            ; To        ; From Clock ;
+-------+--------------+------------+---------------------------------+-----------+------------+
; N/A   ; None         ; 5.000 ns   ; lpm_counter:count_rtl_0|dffs[5] ; clk_div16 ; clk        ;
; N/A   ; None         ; 5.000 ns   ; lpm_counter:count_rtl_0|dffs[4] ; clk_div8  ; clk        ;
; N/A   ; None         ; 5.000 ns   ; lpm_counter:count_rtl_0|dffs[2] ; clk_div4  ; clk        ;
; N/A   ; None         ; 5.000 ns   ; lpm_counter:count_rtl_0|dffs[0] ; clk_div2  ; clk        ;
+-------+--------------+------------+---------------------------------+-----------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 30 15:22:37 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clkdiv -c clkdiv
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 100.0 MHz between source register "lpm_counter:count_rtl_0|dffs[0]" and destination register "lpm_counter:count_rtl_0|dffs[0]" (period= 10.0 ns)
    Info: + Longest register to register delay is 6.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: 2: + IC(0.000 ns) + CELL(6.000 ns) = 6.000 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
        Info: Total cell delay = 6.000 ns ( 100.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 1.500 ns
            Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC1; Fanout = 7; REG Node = 'lpm_counter:count_rtl_0|dffs[0]'
            Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Micro setup delay of destination is 2.000 ns
Info: tco from clock "clk" to destination pin "clk_div16" through register "lpm_counter:count_rtl_0|dffs[5]" is 5.000 ns
    Info: + Longest clock path from clock "clk" to source register is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4; Fanout = 2; REG Node = 'lpm_counter:count_rtl_0|dffs[5]'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 2.000 ns
    Info: + Longest register to pin delay is 1.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'lpm_counter:count_rtl_0|dffs[5]'
        Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'clk_div16'
        Info: Total cell delay = 1.500 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Sep 30 15:22:37 2008
    Info: Elapsed time: 00:00:00