trafficlight.tan.summary

一些很好的FPGA设计实例

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -2.809 ns
From           : Reset
To             : counter55:inst2|CData0[3]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.986 ns
From           : scan:inst|sdata[0]
To             : SEG_Data[2]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 9.004 ns
From           : SW
To             : Yellow2
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.781 ns
From           : Reset
To             : counter55:inst2|CData0[0]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 143.08 MHz ( period = 6.989 ns )
From           : scan:inst|sdata[0]
To             : counter55:inst2|CData0[3]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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