dispdecoder.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 22 行

module dispdecoder(data_in,data_out);
output [7:0] data_out;
input  [3:0] data_in;
reg [7:0] data_out;

always @(data_in)
begin
	case(data_in)
    	4'b0000 : data_out <= 8'b11111100;  //0
		4'b0001 : data_out <= 8'b01100000;  //1
		4'b0010 : data_out <= 8'b11011010;  //2
		4'b0011 : data_out <= 8'b11110010;  //3
		4'b0100 : data_out <= 8'b01100110;  //4
		4'b0101 : data_out <= 8'b10110110;  //5
		4'b0110 : data_out <= 8'b10111110;  //6
		4'b0111 : data_out <= 8'b11100000;  //7
		4'b1000 : data_out <= 8'b11111110;  //8
		4'b1001 : data_out <= 8'b11100110;  //9
		default : data_out <= 8'b00000000;
	endcase
end
endmodule