📄 trafficlight.map.smsg

📁 一些很好的FPGA设计实例

💻 SMSG

字号:

Warning (10268): Verilog HDL information at counter05.v(20): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at counter55.v(19): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fdiv1hz.v(9): Always Construct contains both blocking and non-blocking assignments
Warning (10268): Verilog HDL information at fdiv1khz.v(10): Always Construct contains both blocking and non-blocking assignments

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