dataconvert55.v

一些很好的FPGA设计实例

module dataconvert55(D_IN1,D_IN0,D_OUT1,D_OUT0);

output [3:0] D_OUT1;
output [3:0] D_OUT0;

input [3:0] D_IN1;
input [3:0] D_IN0;

reg [3:0] D_OUT1;
reg [3:0] D_OUT0;
reg [7:0] DATA;

always
begin
	DATA <= 8'b01010101-((D_IN1<<4)+D_IN0);
	if(((DATA>>4)&4'b1111)>4'b0101)
		D_OUT1 <= (DATA>>4)&4'b1111-4'b1111;
	else
		D_OUT1 <= (DATA>>4)&4'b1111;
	if((DATA&4'b1111)>4'b1001)
		D_OUT0 <= (DATA&4'b1111)-4'b0110;
	else
		D_OUT0 <= DATA&4'b1111;
end
endmodule