📄 trafficlight.map.rpt
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; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 92 ;
; -- arithmetic mode ; 68 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 64 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 83 ;
; Total logic cells in carry chains ; 71 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; fdiv1khz:inst12|clk_out ;
; Maximum fan-out ; 34 ;
; Total fan-out ; 610 ;
; Average fan-out ; 3.41 ;
+---------------------------------------------+-------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
; |trafficlight ; 160 (0) ; 83 ; 0 ; 0 ; 19 ; 0 ; 77 (0) ; 2 (0) ; 81 (0) ; 71 (0) ; 0 (0) ; |trafficlight ;
; |control:inst14| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |trafficlight|control:inst14 ;
; |counter05:inst1| ; 8 (8) ; 5 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |trafficlight|counter05:inst1 ;
; |counter55:inst2| ; 30 (30) ; 9 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 0 (0) ; 9 (9) ; 7 (7) ; 0 (0) ; |trafficlight|counter55:inst2 ;
; |datamux:inst6| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |trafficlight|datamux:inst6 ;
; |dispdecoder:inst7| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |trafficlight|dispdecoder:inst7 ;
; |dispmux:inst8| ; 15 (15) ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 (15) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |trafficlight|dispmux:inst8 ;
; |dispselect:inst9| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |trafficlight|dispselect:inst9 ;
; |fdiv1hz:inst11| ; 44 (44) ; 33 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 1 (1) ; 32 (32) ; 32 (32) ; 0 (0) ; |trafficlight|fdiv1hz:inst11 ;
; |fdiv1khz:inst12| ; 44 (44) ; 33 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 1 (1) ; 32 (32) ; 32 (32) ; 0 (0) ; |trafficlight|fdiv1khz:inst12 ;
; |scan:inst| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |trafficlight|scan:inst ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 83 ;
; Number of registers using Synchronous Clear ; 64 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |trafficlight|counter05:inst1|CData0[1] ;
; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |trafficlight|counter55:inst2|CData0[1] ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |trafficlight|counter55:inst2|CData1[3] ;
; 9:1 ; 2 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |trafficlight|dispmux:inst8|Selector0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu May 22 20:57:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off trafficlight -c trafficlight
Info: Found 1 design units, including 1 entities, in source file control.v
Info: Found entity 1: control
Info: Found 1 design units, including 1 entities, in source file counter05.v
Info: Found entity 1: counter05
Info: Found 1 design units, including 1 entities, in source file counter55.v
Info: Found entity 1: counter55
Info: Found 1 design units, including 1 entities, in source file countersel.v
Info: Found entity 1: countersel
Info: Found 1 design units, including 1 entities, in source file dataconvert05.v
Info: Found entity 1: dataconvert05
Info: Found 1 design units, including 1 entities, in source file dataconvert55.v
Info: Found entity 1: dataconvert55
Info: Found 1 design units, including 1 entities, in source file datamux.v
Info: Found entity 1: datamux
Info: Found 1 design units, including 1 entities, in source file dispdecoder.v
Info: Found entity 1: dispdecoder
Info: Found 1 design units, including 1 entities, in source file dispmux.v
Info: Found entity 1: dispmux
Info: Found 1 design units, including 1 entities, in source file dispselect.v
Info: Found entity 1: dispselect
Info: Found 1 design units, including 1 entities, in source file fdiv1hz.v
Info: Found entity 1: fdiv1hz
Info: Found 1 design units, including 1 entities, in source file fdiv1khz.v
Info: Found entity 1: fdiv1khz
Info: Found 1 design units, including 1 entities, in source file scan.v
Info: Found entity 1: scan
Info: Found 1 design units, including 1 entities, in source file trafficlight.bdf
Info: Found entity 1: trafficlight
Info: Elaborating entity "trafficlight" for the top level hierarchy
Info: Elaborating entity "control" for hierarchy "control:inst14"
Info: Elaborating entity "scan" for hierarchy "scan:inst"
Info: Elaborating entity "counter55" for hierarchy "counter55:inst2"
Warning (10230): Verilog HDL assignment warning at counter55.v(37): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter55.v(42): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter55.v(59): truncated value with size 8 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter55.v(61): truncated value with size 8 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter55.v(63): truncated value with size 8 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter55.v(65): truncated value with size 8 to match size of target (4)
Info: Elaborating entity "fdiv1hz" for hierarchy "fdiv1hz:inst11"
Info: Elaborating entity "fdiv1khz" for hierarchy "fdiv1khz:inst12"
Info: Elaborating entity "countersel" for hierarchy "countersel:inst3"
Info: Elaborating entity "counter05" for hierarchy "counter05:inst1"
Warning (10230): Verilog HDL assignment warning at counter05.v(32): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter05.v(49): truncated value with size 8 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at counter05.v(51): truncated value with size 8 to match size of target (4)
Info: Elaborating entity "dispdecoder" for hierarchy "dispdecoder:inst7"
Info: Elaborating entity "dispmux" for hierarchy "dispmux:inst8"
Info (10264): Verilog HDL Case Statement information at dispmux.v(14): all case item expressions in this case statement are onehot
Info: Elaborating entity "datamux" for hierarchy "datamux:inst6"
Info: Elaborating entity "dispselect" for hierarchy "dispselect:inst9"
Info: Duplicate registers merged to single register
Info: Duplicate register "counter05:inst1|CData1[0]" merged to single register "counter05:inst1|CData1[3]"
Info: Duplicate register "counter05:inst1|CData1[2]" merged to single register "counter05:inst1|CData1[3]"
Info: Duplicate register "counter05:inst1|CData1[1]" merged to single register "counter05:inst1|CData1[3]"
Warning: Reduced register "counter05:inst1|CData1[3]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "dispselect:inst9|D_OUT[1]" merged to single register "dispselect:inst9|D_OUT[0]", power-up level changed
Warning: Output pins are stuck at VCC or GND
Warning: Pin "SEG_Data[0]" stuck at GND
Info: Implemented 179 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 16 output pins
Info: Implemented 160 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Processing ended: Thu May 22 20:57:22 2008
Info: Elapsed time: 00:00:07
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/图书光盘/《Verilog HDL数字控制系统设计实例》-冼进-源代码/交通灯控制系统/第5章/trafficlight.map.smsg.
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