countersel.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 24 行

module countersel(D_IN,D_OUT1,D_OUT0);

output D_OUT1;
output D_OUT0;

input  [1:0] D_IN;

reg D_OUT1;
reg D_OUT0;

always
begin
	case(D_IN)
		2'b00 : {D_OUT1,D_OUT0} <= 2'b10;
		2'b01 : {D_OUT1,D_OUT0} <= 2'b01;
		2'b10 : {D_OUT1,D_OUT0} <= 2'b10;
		2'b11 : {D_OUT1,D_OUT0} <= 2'b01;
		default : {D_OUT1,D_OUT0} <= 2'b00;
	endcase
end
endmodule