spwm.vhd

一些很好的FPGA设计实例

--文件名：spwm.vhd

--功  能：spwm调制

--说  明：测试时用示波器接全桥逆变控制信号的正负（zheng,fu)输出端，便可观察到

--        SPWM调制波形的输出

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity spwm is
    generic(max_freq:integer:=1000);     --spwm输出的最大频率(50kHz)
    Port (clk:in std_logic;              --系统晶振频率输入
	     reset1:in std_logic;           --spwm控制的复位信号
	     fadd,fsub:in std_logic;        --spwm控制的频率增大和减小输入
	     zheng,fu:out std_logic);       --全桥逆变控制信号输出
end spwm;

architecture Behavioral of spwm is
type states is (st0,st1,st2,st3,st4,st5,st6);
signal state:states:=st0;
signal new_clk:std_logic;
signal s:integer:=0;
signal e:std_logic:='0';
signal zf:std_logic;
begin

pro0:process(fadd,fsub,s,clk,state,reset1)
variable s1:integer:=0;
variable cnt:integer:=0;
begin
 if reset1='1' then
  if rising_edge(clk) then
     cnt:=cnt+1;                      --按键防抖动计数
     case state is                      --状态机控制禁止按键连击
	    when st0=>if fsub='0' and fadd='1' then state<=st1;
		           elsif fadd='0' and fsub='1' then state<=st3;
		           else state<=st0;
				     end if;
		 when st1=>if fsub='1' then state<=st2; cnt:=0;
		           else state<=st1;
				     end if;
	    when st2=>if cnt>=1000000 then state<=st5;       --延时
	              else state<=st2;
				     end if;
		 when st3=>if fadd='1' then state<=st4; cnt:=0;
		           else state<=st3;
				     end if;
	    when st4=>if cnt>=1000000 then state<=st6;       --延时
	              else state<=st4;
				     end if;
       when st5=>if s1>31998720 then s1:=31998720;
	              else s1:=s1+100;                --按键每次步进分频系数为100
	              end if; state<=st0;
       when st6=>if s1<1 then s1:=0;
	              else s1:=s1-100;
	              end if; state<=st0;
       when others=>state<=st0;
	  end case;
  end if;
 else s1:=0;
 end if;
s<=s1;
end process;

pro1:process(clk,s)
variable count:integer:=0;
begin
  if rising_edge(clk) then     
     if count>=max_freq+s then new_clk<='1'; count:=0;
	  else count:=count+1; new_clk<='0';            --输出信号频率控制
	  end if;
  end if;
end process;

pro2:process(new_clk,s,zf)
variable cnt:integer:=0;
begin
  if rising_edge(new_clk) then
     cnt:=cnt+1;                                 --spwm调制查表
     if cnt<6 then zf<='0';
	  elsif cnt<7 then zf<='1';
	  elsif cnt<19 then zf<='0';
	  elsif cnt<23 then zf<='1';
	  elsif cnt<34 then zf<='0';
	  elsif cnt<41 then zf<='1';
	  elsif cnt<51 then zf<='0';
	  elsif cnt<61 then zf<='1';
	  elsif cnt<70 then zf<='0';
	  elsif cnt<81 then zf<='1';
	  elsif cnt<88 then zf<='0';
	  elsif cnt<100 then zf<='1';
	  elsif cnt<104 then zf<='0';
	  elsif cnt<117 then zf<='1';
	  elsif cnt<118 then zf<='0';
	  elsif cnt<126 then zf<='1';
	  elsif cnt<134 then zf<='1';
	  elsif cnt<135 then zf<='0';
	  elsif cnt<148 then zf<='1';
	  elsif cnt<152 then zf<='0';
	  elsif cnt<164 then zf<='1';
	  elsif cnt<171 then zf<='0';
	  elsif cnt<182 then zf<='1';
	  elsif cnt<191 then zf<='0';
	  elsif cnt<201 then zf<='1';
	  elsif cnt<211 then zf<='0';
	  elsif cnt<218 then zf<='1';
	  elsif cnt<229 then zf<='0';
	  elsif cnt<233 then zf<='1';
	  elsif cnt<245 then zf<='0';
	  elsif cnt<246 then zf<='1';
	  elsif cnt<252 then zf<='0';
	  else cnt:=0; e<=(not e);
	  end if;
  end if;
end process;

pro3:process(e,zf)
begin
  if e='0' then zheng<=zf; fu<='0';                --输出spwm调制信号
  else fu<=zf; zheng<='0';
  end if;
end process;
end Behavioral;