counter6.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter6 is
    Port ( clk : in std_logic;    --时钟信号输入端口
         preset : in std_logic;   --复位信号
         din : in std_logic_vector(2 downto 0);    --3位二进制数据输入
         dout : out std_logic_vector(3 downto 0);  --3位二进制数据输出
		 c:out std_logic);          --进位位的输出
end counter6;
architecture Behavioral of counter6 is
signal count : std_logic_vector(2 downto 0);   --定义一个三位二进制信号
begin
    dout <= '0'&count;
	process(clk,preset,din)
	begin
	   if preset= '1' then
		  count <= din;
		  c<='0';       --复位信号为低电平'0'时，输入数据赋值给count，进位位清零
       elsif rising_edge(clk) then    --否则，当时钟信号为上升沿时执行then后面的指令
		   if count>="101" then
			   count<="000";
			   c<='1';    --计数到5时，count清零，进位位赋1
           else          --否则，计数加1，进位位赋0
			   count<=count+1;
			   c<='0';
          end if;
      end if;	
   end process;
end Behavioral;