divice.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity divice is
    Port ( clk : in std_logic;
           reset : in std_logic;
           clk_1hz : out std_logic);
end divice;

architecture Behavioral of divice is
signal q :integer range 0 to 25000000;         --秒分频系数 
signal clkr :std_logic; 
begin
process(clk)                     --此进程产生一个持续时间为一秒的的闸门信号 
begin
  if reset='1' then q<=0; clk_1hz<='0';	clkr<='0';
  elsif clk'event and clk='1' then 
     if q<24999999 then q<=q+1;
     elsif q=24999999 then 
	  q<=0;
	  clkr<=not clkr;
     end if;
  end if;
 clk_1hz<=clkr	;
 
end process;

end Behavioral;