counter10.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;   --标准VHDL语言库
entity counter10 is
    Port ( clk : in std_logic;         --时钟信号输入
          preset : in std_logic;       --复位信号输入
          din : in std_logic_vector(3 downto 0);    --数据输入
          dout : out std_logic_vector(3 downto 0);    --数据输出
		  c:out std_logic);            --进位
end counter10;
architecture Behavioral of counter10 is
   signal count : std_logic_vector(3 downto 0);     --定义一个4位二进制信号count
begin
    dout <= count;
	process(clk,preset,din)    --进程
	begin
	   if preset='1'then
		 count <= din ;
		 c<='0';        --复位时把输入数据赋值给count，进位位清零
       elsif rising_edge(clk) then     --当时钟上升沿来时，执行then后面的指令
		   if count >= "1001" then
			   count <= "0000";
			   c<='1';        --计数到九时，count清零，进位位赋1；
           else              --否则计数加1，进位位赋1
			   count <= count+1;
			   c<='0';
           end if;
      end if;
    end process;
end Behavioral;