clock.vhd

一些很好的FPGA设计实例

--------*******************电子时钟*******************--------

--文件名：clock.vhd

--功  能：带预制数的电子时钟

--说  明：利用动态显示原理把时间送数码管显示；并可实现

--时间的预置；复位信号用拨盘开关的右边第一个来控制（高电平有效），

--拨下为高电平；select_dis的功能用右边第二个表示；数据预置信号用

--用右边第三个拨盘开关实现，hourh，hourl，minh，minl，secondh，secondl

--分别锁在按键S4,S3,S7,S0,S9,S8上；使用这些按键可实现小时分秒的设置；

--具体的锁脚请看锁脚文件

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port ( clk : in std_logic;                   --系统时间
           reset : in std_logic;                   --复位信号
           preset : in std_logic;  --复位预置数据的信号
	      select_dis : in std_logic;	--选择数码管显示的是小时和分钟还是分钟与秒钟
	      hourh : in std_logic;  --小时高位的数据输入
           hourl : in std_logic;  --小时低位的数据输入
           minh : in std_logic;   --分钟高位的数据输入
           minl : in std_logic;   --分钟低位的数据输入
           secondh : in std_logic;	    --秒钟高位的数据输入
           secondl : in std_logic;	    --秒钟低位的数据输入
		 cs : out std_logic_vector(1 downto 0);
           shift : out std_logic_vector(3 downto 0);
           data_led : out std_logic_vector(7 downto 0));
end clock;
architecture Behavioral of clock is
component preset_cnt is
 Port ( clk : in std_logic;    --系统时钟输入
           reset : in std_logic;
		 preset : in std_logic;  --复位预置数据的信号
           hourh : in std_logic;  --小时高位的数据输入
           hourl : in std_logic;  --小时低位的数据输入
           minh : in std_logic;   --分钟高位的数据输入
           minl : in std_logic;   --分钟低位的数据输入
           secondh : in std_logic;	    --秒钟高位的数据输入
           secondl : in std_logic;	    --秒钟低位的数据输入
		  houroh : out std_logic_vector(1 downto 0);   --小时高位的数据输出
           hourol : out std_logic_vector(3 downto 0);   --小时低位的数据输出
           minoh : out std_logic_vector(2 downto 0);   --分钟高位的数据输出
           minol : out std_logic_vector(3 downto 0);   --分钟低位的数据输出
           secondoh : out std_logic_vector(2 downto 0);   --秒钟高位的数据输出
           secondol : out std_logic_vector(3 downto 0));
end component;
component divice is
Port ( clk : in std_logic;
           reset : in std_logic;
           clk_1hz : out std_logic);
end component;

   component counter10 is
	Port ( clk : in std_logic;
         preset : in std_logic;
         din : in std_logic_vector(3 downto 0);
         dout : out std_logic_vector(3 downto 0);
		 c:out std_logic);
end component;

	component counter6 is
	Port ( clk : in std_logic;
         preset : in std_logic;
         din : in std_logic_vector(2 downto 0);
         dout : out std_logic_vector(3 downto 0);
		 c:out std_logic);
	end component;

	component counter24 is
	 Port ( clk : in std_logic;
          preset : in std_logic;
          din : in std_logic_vector(5 downto 0);
          dout : out std_logic_vector(7 downto 0));
	end component;

component dynamic_display is
     Port ( clk : in std_logic;
           reset : in std_logic;
           hourh : in std_logic_vector(3 downto 0);
           hourl : in std_logic_vector(3 downto 0);
           minh : in std_logic_vector(3 downto 0);
           minl : in std_logic_vector(3 downto 0);
           secondh : in std_logic_vector(3 downto 0);
           secondl : in std_logic_vector(3 downto 0);
           select_dis : in std_logic;
           cs : out std_logic_vector(1 downto 0);
           shift : out std_logic_vector(3 downto 0);
           data_led : out std_logic_vector(7 downto 0));
end component;

	signal c1,c2,c3,c4,clk1:std_logic;
	signal dinsl,dinml:std_logic_vector(3 downto 0);
	signal dinsh,dinmh:std_logic_vector(2 downto 0);
	signal dinh:std_logic_vector(5 downto 0);
	signal doutsl,doutsh,doutml,doutmh:std_logic_vector(3 downto 0);
	signal douth:std_logic_vector(7 downto 0);

begin
u1:preset_cnt port map (clk=>clk,reset=>reset,preset=>preset,hourh=>hourh,hourl=>hourl,minh=>minh,minl=>minl,
    secondh=>secondh,secondl=>secondl,houroh=>dinh(5 downto 4),hourol=>dinh(3 downto 0),
    minoh=>dinmh,minol=>dinml,secondoh=>dinsh,secondol=>dinsl);
u2: counter10 port map( clk=>clk1, preset=>preset,din=>dinsl,dout=>doutsl,c=>c1);
u3: counter6 port map( clk=>c1,preset=>preset,din=>dinsh,dout=>doutsh,c=>c2);
u4: counter10 port map(	clk=>c2,preset=>preset,din=>dinml,dout=>doutml,c=>c3);
u5: counter6 port map( clk=>c3,preset=>preset,din=>dinmh,dout=>doutmh,c=>c4);
u6: counter24 port map( clk=>c4,preset=>preset,din=>dinh,dout=>douth);
u7: divice port map(clk=>clk,reset=>reset, clk_1hz=>clk1);
u8: dynamic_display port map (clk=>clk,reset=>reset,hourh=>douth(7 downto 4),hourl=>douth(3 downto 0),
    minh=>doutmh,minl=>doutml,secondh=>doutsh,secondl=>doutsl,select_dis=>select_dis,cs=>cs,
    shift=>shift,data_led=>data_led);
end Behavioral;