lcd.twr

来自「一些很好的FPGA设计实例」· TWR 代码 · 共 43 行

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Release 8.1i Trace I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise lcd240128_ok.ise -intstyle ise -e 3 -l 3 -s 7
-xml LCD LCD.ncd -o LCD.twr LCD.pcf


Design file:              lcd.ncd
Physical constraint file: lcd.pcf
Device,speed:             xc2s100e,-7 (PRODUCTION 1.18 2005-11-04)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    5.751|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Tue Jun 20 09:11:28 2006
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Peak Memory Usage: 92 MB