lcd.par

一些很好的FPGA设计实例

Release 8.1i par I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

TANGMEIXUAN::  Tue Jun 20 09:08:18 2006

par -w -intstyle ise -ol std -t 1 LCD_map.ncd LCD.ncd LCD.pcf 


Constraints file: LCD.pcf.
Loading device for application Rf_Device from file '2s100e.nph' in environment D:\Xilinx.
   "LCD" is an NCD, version 3.1, device xc2s100e, package pq208, speed -7

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000 Celsius)
Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.18 2005-11-04".


Device Utilization Summary:

   Number of GCLKs                     2 out of 4      50%
   Number of External GCLKIOBs         1 out of 4      25%
      Number of LOCed GCLKIOBs         1 out of 1     100%

   Number of External IOBs            22 out of 142    15%
      Number of LOCed IOBs            22 out of 22    100%

   Number of SLICEs                  239 out of 1200   19%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989d40) REAL time: 45 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 45 secs 

Phase 3.23
Phase 3.23 (Checksum:1c9c37d) REAL time: 45 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 45 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 45 secs 

Phase 6.8
............
.............
..................
...................................
..............................
....
Phase 6.8 (Checksum:9f8ead) REAL time: 52 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 52 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 56 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 56 secs 

Writing design to file LCD.ncd


Total REAL time to Placer completion: 59 secs 
Total CPU time to Placer completion: 15 secs 

Starting Router

Phase 1: 1775 unrouted;       REAL time: 1 mins 2 secs 

Phase 2: 1680 unrouted;       REAL time: 1 mins 10 secs 

Phase 3: 480 unrouted;       REAL time: 1 mins 12 secs 

Phase 4: 480 unrouted; (0)      REAL time: 1 mins 12 secs 

Phase 5: 488 unrouted; (0)      REAL time: 1 mins 13 secs 

Phase 6: 0 unrouted; (0)      REAL time: 1 mins 15 secs 

Phase 7: 0 unrouted; (0)      REAL time: 1 mins 16 secs 

Phase 8: 0 unrouted; (0)      REAL time: 1 mins 16 secs 

Total REAL time to Router completion: 1 mins 17 secs 
Total CPU time to Router completion: 23 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|            clk_100k |      GCLKBUF1| No   |   67 |  0.133     |  0.447      |
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      GCLKBUF0| No   |   10 |  0.002     |  0.330      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.363
   The MAXIMUM PIN DELAY IS:                               7.756
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.820

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
         755         700         219          33          50           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of  
                                            |            |            | Levels | Slack      |errors     
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 11.864ns   | 7      | N/A        | N/A       
  _100k                                     |            |            |        |            |           
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 5.751ns    | 4      | N/A        | N/A       
  _BUFGP                                    |            |            |        |            |           
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 26 secs 
Total CPU time to PAR completion: 24 secs 

Peak Memory Usage:  108 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file LCD.ncd



PAR done!