uart.vhd

一些很好的FPGA设计实例

--文件名：UART.VHD

--功  能：RS232通信

--说  明：该程序包含了波特率发生器、数据发生器、数据接收器3个部分
         
--        和电脑连接起来通过“串口调试助手”可以测试数据的接收和发送

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity uart is

     generic(ff:integer:=8);

     Port (cs: out std_logic_vector(1 downto 0);	  --位选数码管和发光二极管
	      clk : in std_logic;				  --系统时钟
           reset : in std_logic;				  --复位信号
           set: in std_logic;					  --设置信号
		 cn : in std_logic;					  --数据发送使能
           rver: in std_logic;				  --RS232的信号接收端
		 data2: out std_logic_vector(7 downto 0); --送出的8位数据
		 txd : out std_logic);				  --RS232的信号发送端
end uart;

architecture Behavioral of uart is

type state1 is(t_indle,t_start,t_wait,t_shift,t_stop);
signal c_state:state1;

type state2 is (r_start,r_center,r_wait,r_sample,r_stop);
signal h_state: state2;

signal data1 : std_logic_vector(8 downto 0);
signal clk1,clk2: std_logic;
signal rver_synt:std_logic;

begin

bxfsq:process(clk,reset)	  --波特率发生器
variable clk0: std_logic;
variable count : integer range 0 to 325;
begin
   if reset='0' then count:=0;clk0:='0';
   elsif clk'event and clk='1' then 
      if count=325 then count:=0;clk0:='1';
      else count:=count+1; clk0:='0';
      end if;
   end if;

    clk1<=clk0;

end process;

pulze1:process(clk,reset)
variable clk0: std_logic;
variable count :integer range 0 to 2500000;
begin
   if reset='0' then clk0:='0';count:=0;
   elsif clk'event and clk='1' then count:=count+1;
      if count=1250000 then clk0:='1';
      elsif count=2500000 then clk0:='0'; count:=0;
      end if;
   end if;

clk2<=clk0;

end process;

leijia: process(clk2,reset,set)	      --数据累加器
variable c: integer range 0 to 50000;
variable data: std_logic_vector(7 downto 0);
begin
   if reset='0' then data:="00000000";
   elsif clk2'event and clk2='1' then 
      if set='0' then  c:=c+1;
	    if c=1  then  data:=data+"00000001"; 
   	    end if;
	 else  c:=0;			 
	 end if;
   end if;

	data1<='1'&data;

end process;

transfer:process(clk1,reset,cn,data1)	      --数据发送部分
variable count1:std_logic_vector(4 downto 0);
variable ff1: integer range 0 to 8;
variable txds: std_logic;
begin
   if reset='0' then c_state<=t_indle;txds:='1'; 
   elsif clk1'event and clk1='1' then 	 
      case c_state is
      when t_indle=>
	               if cn='1' then c_state<=t_start;
                    else c_state<=t_indle;
				end if;

      when t_start=> 
	               if count1="00100" then c_state<=t_wait; count1:="00000";
                    else count1:=count1+1; c_state<=t_start;txds:='0';
     			end if;

      when t_wait=>  
	               if count1="01110" then 
                       if ff1=ff then c_state<=t_stop; ff1:=0;
				   else c_state<=t_shift;
                       end if; count1:="00000";
				else count1:=count1+1;c_state<=t_wait;
				end if;

      when t_shift=>
	                  txds:=data1(ff1);c_state<=t_wait;ff1:=ff1+1;

      when t_stop =>
	               if count1="01110" then 
                       if cn='0' then c_state<=t_indle;count1:="00000";
				   else count1:=count1;c_state<=t_stop; 
				   end if; count1:="00000";
				else count1:=count1+1;c_state<=t_stop;txds:='1';
				end if;

      when others=>c_state<=t_indle;
      end  case;
   end if;

txd<=txds;

end process;

gz:process(clk,rver)
begin
   if clk'event and clk='1' then
     if rver='1' then rver_synt<='1';
     else rver_synt<='0';
	end if;
   end if;
end process;

recevier:process(clk1,reset,rver_synt)		     --数据接收部分
variable c1: std_logic_vector(4 downto 0) ;
variable c2: integer range 0 to 8;
variable data3:std_logic_vector(7 downto 0);
begin
   if reset='0' then h_state<=r_start;data3:="11111111"; cs<="11"; data2<="11111111";
   elsif clk1'event and clk1='1' then 	cs<="10";
      case h_state is
      when r_start=> 
	               if rver_synt='0' then h_state<=r_center;    
                    else  h_state<=r_start;  
                    end if;

     when r_center=> 
	               if c1="00100" then h_state<=r_wait;c1:="00000";
                    else c1:=c1+1; h_state<=r_center;
				end if;

     when r_wait=> 
	               if c1="01110" then 
				   if c2=ff  then h_state<=r_stop; c1:="00000";	c2:=0;
                       else  h_state<=r_sample;
                       end if;

                       c1:="00000";

                    else c1:=c1+1; h_state<=r_wait;
                    end if;

     when r_sample=>
	               data3(c2):=rver_synt;c2:=c2+1; h_state<=r_wait;

     when r_stop=> 
	               h_state<=r_start;data2<=data3(7 downto 0);
					
     when others=>  h_state<=r_start;
     end case;
  end if;
end process;
end;