top_traffic_light1.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--该交通灯系统实现交通灯的正常控制并显示倒计时时间，reset输入信号接拨盘开关的
--第八个键，对交通灯进行复位清零操作；data_led是数据的输出，利用动态显示的原理同时
--用发光二极管显示交通灯的灯亮的状态和用数码管显示倒计时的时间。shift4是数码管
--的位选信号，选通所要显示的数码管。

entity top_traffic_light1 is
    Port ( clk : in std_logic;
           reset : in std_logic;
           cs : out std_logic_vector(1 downto 0);	--数码管和发光二极管的片选信号
           data_led : out std_logic_vector(7 downto 0);--最终送数据总线的数据
           shift4 : out std_logic_vector(3 downto 0));  --数码管的位选信号
end top_traffic_light1;

architecture Behavioral of top_traffic_light1 is
component state_machine 	is
  Port ( clk:in std_logic;
	      reset : in std_logic;
		   clk_1hz:out std_logic;
		   dataout1,dataout2: out std_logic_vector(3 downto 0);
         data_ledfa : out std_logic_vector(7 downto 0 ));
end component state_machine;
component dynamic_display is
Port ( clk : in std_logic; 
		 reset: in std_logic; 
		 datain1,datain2: in std_logic_vector(3 downto 0);
		 data_ledfa:in std_logic_vector(7 downto 0 );
		 cs:out std_logic_vector(1 downto 0);
	    shift: out std_logic_vector(3 downto 0);
       led : out std_logic_vector(7 downto 0));
end component dynamic_display;
component yellowflash is
Port ( f_1hz : in std_logic;
	    in_yellow:in std_logic;
       out_yellow : out std_logic);
end component yellowflash;
signal dataout1,dataout2:  std_logic_vector(3 downto 0);
signal data_ledfa: std_logic_vector(7 downto 0 );
signal clk_1hz: std_logic;
signal in_yellow1,in_yellow2: std_logic;
signal out_yellow1,out_yellow2 :  std_logic;
begin
u1: state_machine port map (clk=>clk,reset=>reset,clk_1hz=>clk_1hz,data_ledfa(3)=>in_yellow2,
    data_ledfa(0)=>in_yellow1,data_ledfa(7 downto 4)=>data_ledfa(7 downto 4),data_ledfa(2 downto 1)=>data_ledfa(2 downto 1),
    dataout1=>dataout1,dataout2=>dataout2);
u2: dynamic_display port map (clk=>clk,reset=>reset,datain1=>dataout1,datain2=>dataout2 ,data_ledfa(3)=>out_yellow2,
    data_ledfa(0)=>out_yellow1,data_ledfa(7 downto 4)=>data_ledfa(7 downto 4),data_ledfa(2 downto 1)=>data_ledfa(2 downto 1),
    cs=>cs,shift=>shift4,led=>data_led);
u3: yellowflash port map (f_1hz=>clk_1hz,in_yellow=>in_yellow1,out_yellow=>out_yellow1);
u4: yellowflash port map (f_1hz=>clk_1hz,in_yellow=>in_yellow2,out_yellow=>out_yellow2);
end Behavioral;