dvif.vhd

一些很好的FPGA设计实例

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 系统分频；

entity dvif is
    Port (clk : in std_logic;
	       clk1k : out std_logic;
	       clk1 : out std_logic;   --1Hz;
			 clk10 : out std_logic); --10Hz;
end dvif;

architecture Behavioral of dvif is
component div_50 
    Port (iclk : in  std_logic;
	       oclk : out std_logic);
end component;

component div_10 
    Port (iclk : in  std_logic;
	       oclk : out std_logic);
end component;

signal clk_1m,clk_100k,clk_10k,clk_1k,clk_100,clk_10 : std_logic;

begin

u1 : div_50 port map(iclk=>clk,oclk=>clk_1m);
u2 : div_10 port map(iclk=>clk_1m,oclk=>clk_100k);
u3 : div_10 port map(iclk=>clk_100k,oclk=>clk_10k);
u4 : div_10 port map(iclk=>clk_10k,oclk=>clk_1k);
u5 : div_10 port map(iclk=>clk_1k,oclk=>clk_100);
u6 : div_10 port map(iclk=>clk_100,oclk=>clk_10);
u7 : div_10 port map(iclk=>clk_10,oclk=>clk1);

clk10<=clk_10;
clk1k<=clk_1k;
end Behavioral;