simple_fsm.tan.rpt

一些很好的FPGA设计实例

; N/A   ; None              ; 8.381 ns        ; b    ; x  ;
+-------+-------------------+-----------------+------+----+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.572 ns ; d    ; pr_state ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------------------------------------------------------------+
; Minimum tco                                                                    ;
+---------------+------------------+----------------+----------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From     ; To ; From Clock ;
+---------------+------------------+----------------+----------+----+------------+
; N/A           ; None             ; 7.230 ns       ; pr_state ; x  ; clk        ;
+---------------+------------------+----------------+----------+----+------------+


+-----------------------------------------------------------------+
; Minimum tpd                                                     ;
+---------------+-------------------+-----------------+------+----+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+----+
; N/A           ; None              ; 8.381 ns        ; b    ; x  ;
; N/A           ; None              ; 8.473 ns        ; a    ; x  ;
+---------------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu May 17 11:46:17 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off simple_fsm -c simple_fsm --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 422.12 MHz between source register pr_state and destination register pr_state
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.616 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
            Info: 2: + IC(0.393 ns) + CELL(0.223 ns) = 0.616 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
            Info: Total cell delay = 0.223 ns ( 36.20 % )
            Info: Total interconnect delay = 0.393 ns ( 63.80 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.780 ns
                Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
                Info: Total cell delay = 1.629 ns ( 58.60 % )
                Info: Total interconnect delay = 1.151 ns ( 41.40 % )
            Info: - Longest clock path from clock clk to source register is 2.780 ns
                Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
                Info: Total cell delay = 1.629 ns ( 58.60 % )
                Info: Total interconnect delay = 1.151 ns ( 41.40 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register pr_state (data pin = d, clock pin = clk) is 2.682 ns
    Info: + Longest pin to register delay is 5.452 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_D9; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(3.660 ns) + CELL(0.705 ns) = 5.452 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.792 ns ( 32.87 % )
        Info: Total interconnect delay = 3.660 ns ( 67.13 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock clk to destination register is 2.780 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.629 ns ( 58.60 % )
        Info: Total interconnect delay = 1.151 ns ( 41.40 % )
Info: tco from clock clk to destination pin x through register pr_state is 7.230 ns
    Info: + Longest clock path from clock clk to source register is 2.780 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.629 ns ( 58.60 % )
        Info: Total interconnect delay = 1.151 ns ( 41.40 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.294 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: 2: + IC(0.407 ns) + CELL(0.366 ns) = 0.773 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'
        Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 4.294 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'
        Info: Total cell delay = 2.770 ns ( 64.51 % )
        Info: Total interconnect delay = 1.524 ns ( 35.49 % )
Info: Longest tpd from source pin a to destination pin x is 8.473 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B8; Fanout = 1; PIN Node = 'a'
    Info: 2: + IC(3.682 ns) + CELL(0.183 ns) = 4.952 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'
    Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 8.473 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'
    Info: Total cell delay = 3.674 ns ( 43.36 % )
    Info: Total interconnect delay = 4.799 ns ( 56.64 % )
Info: th for register pr_state (data pin = d, clock pin = clk) is -2.572 ns
    Info: + Longest clock path from clock clk to destination register is 2.780 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.629 ns ( 58.60 % )
        Info: Total interconnect delay = 1.151 ns ( 41.40 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.452 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_D9; Fanout = 1; PIN Node = 'd'
        Info: 2: + IC(3.660 ns) + CELL(0.705 ns) = 5.452 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.792 ns ( 32.87 % )
        Info: Total interconnect delay = 3.660 ns ( 67.13 % )
Info: Minimum tco from clock clk to destination pin x through register pr_state is 7.230 ns
    Info: + Shortest clock path from clock clk to source register is 2.780 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_L7; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(1.151 ns) + CELL(0.542 ns) = 2.780 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: Total cell delay = 1.629 ns ( 58.60 % )
        Info: Total interconnect delay = 1.151 ns ( 41.40 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Shortest register to pin delay is 4.294 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y30_N4; Fanout = 2; REG Node = 'pr_state'
        Info: 2: + IC(0.407 ns) + CELL(0.366 ns) = 0.773 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'
        Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 4.294 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'
        Info: Total cell delay = 2.770 ns ( 64.51 % )
        Info: Total interconnect delay = 1.524 ns ( 35.49 % )
Info: Shortest tpd from source pin b to destination pin x is 8.381 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C9; Fanout = 1; PIN Node = 'b'
    Info: 2: + IC(3.698 ns) + CELL(0.075 ns) = 4.860 ns; Loc. = LC_X36_Y30_N2; Fanout = 1; COMB Node = 'x~8'
    Info: 3: + IC(1.117 ns) + CELL(2.404 ns) = 8.381 ns; Loc. = PIN_E9; Fanout = 0; PIN Node = 'x'
    Info: Total cell delay = 3.566 ns ( 42.55 % )
    Info: Total interconnect delay = 4.815 ns ( 57.45 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu May 17 11:46:18 2007
    Info: Elapsed time: 00:00:01