simple_fsm.vhd

一些很好的FPGA设计实例

-------------整个设计包括两个状态（a，b），每次当发现d='1'时，他都会从当前状态
-------------跳变到另一个状态，当状态机处于state a时，输出端口x=a,当状态机处于state b时，输出端口x=b
------------------------------------------------
entity simple_fsm is 
port(a,b,c,d,clk,rst : in bit;
     x: out bit);
end simple_fsm;
----------------------------
architecture simple_fsm of simple_fsm is
    type state is (statea,stateb);
signal pr_state,nx_state : state;
begin
-----------------lower section-------------------------------
process( rst,clk)
begin 
  if (rst = '1')then
   pr_state <= statea;
  elsif (clk 'event and clk = '1')then
   pr_state <= nx_state;
  end if;
end process;
-----------------upper section-------------------
process (a,b,c,d,pr_state)
begin
  case pr_state is 
   when  statea => 
   x <= a;
   if (d = '1')then nx_state <= stateb;
   else nx_state <= statea;
   end if;
 when  stateb => 
   x <= b;
   if (d = '1')then nx_state <= statea;
   else nx_state <= stateb;
   end if;
  end case;
end process;
end simple_fsm;