有限状态机设计风格模板#2.vhd

一些很好的FPGA设计实例

---------------------------有限状态机设计风格模板#2
--在很多应用中，需要同步的寄存器输出，输出信号只有在示众边沿出现时才能够更新。，此时输出
--必须先使用寄存器存储起来，可以使用辅助信号temp来计算电路的输出值，但它的值只能在某个
-- 时钟边沿出现时才传递给真正的输出信号
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity <ent_name> is
   port(input: in <data_type>;
        reset,clock：in std_logic;
         output: out <data_state>);
end <ent_name>;
-------------------------------
architecture <arch_name> of <ent_name> is
   type state is (state0,state1,state2,state3,...);
   signal pr_state,nx_state: states;
   signal temp : <data_type>;
begin
--------------------lower section------------------
process (reset,colock)
begin
  if(reset = '1')then
     pr_state <= state0;
  elsif (clock 'event and clock = '1')then
  output <= temp;
  pr_state <= nx_state;
  end if;
end process;
-----------------------upper section----------------
process ( pr_state)
begin
  case pr_state is
  when state0 =>
    temp <= <value>;
    if(condition) then nx_state <= state1;
...
    end if;
  when state1 =>
    temp <= <value>;
    if(condition) then nx_state <= state2;
...
    end if;
  when state2 =>
    temp <= <value>;
    if(condition) then nx_state <= state3;
...
    end if;
............
  end case;;
end process;
end <arch_name>;