parity_det.map.eqn

一些很好的FPGA设计实例

--A1L21 is temp~46
--operation mode is normal

A1L21 = input[1] $ input[6] $ input[0] $ input[5];


--A1L31 is temp~47
--operation mode is normal

A1L31 = input[3] $ input[4];


--A1L11 is temp~6
--operation mode is normal

A1L11 = A1L21 $ A1L31 $ input[7] $ input[2];


--input[1] is input[1]
--operation mode is input

input[1] = INPUT();


--input[6] is input[6]
--operation mode is input

input[6] = INPUT();


--input[0] is input[0]
--operation mode is input

input[0] = INPUT();


--input[5] is input[5]
--operation mode is input

input[5] = INPUT();


--input[3] is input[3]
--operation mode is input

input[3] = INPUT();


--input[4] is input[4]
--operation mode is input

input[4] = INPUT();


--input[7] is input[7]
--operation mode is input

input[7] = INPUT();


--input[2] is input[2]
--operation mode is input

input[2] = INPUT();


--output is output
--operation mode is output

output = OUTPUT(A1L11);