parity_det.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 20 行

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entity parity_det is
   generic (n: integer := 7);
   port (input: in bit_vector(n downto 0);
       output: out bit);
end parity_det;
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architecture parity of parity_det is
begin 
process (input)
  variable temp: bit;
  begin
  temp :='0';
  for i in input 'range loop
    temp :=temp xor input (i);
   end loop;
   output <= temp;
end process;
end parity;