fuyongqi.tan.rpt

一些很好的FPGA设计实例

Timing Analyzer report for fuyongqi
Sat May 12 16:20:28 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Settings
  3. Timing Analyzer Summary
  4. tpd
  5. Minimum tpd
  6. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1S10F484C5       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 9.282 ns    ; s0   ; y  ;            ;          ; 0            ;
; Worst-case Minimum tpd       ; N/A   ; None          ; 8.190 ns    ; a    ; y  ;            ;          ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 9.282 ns        ; s0   ; y  ;
; N/A   ; None              ; 9.159 ns        ; c    ; y  ;
; N/A   ; None              ; 8.676 ns        ; d    ; y  ;
; N/A   ; None              ; 8.479 ns        ; s1   ; y  ;
; N/A   ; None              ; 8.190 ns        ; a    ; y  ;
+-------+-------------------+-----------------+------+----+


+-----------------------------------------------------------------+
; Minimum tpd                                                     ;
+---------------+-------------------+-----------------+------+----+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+----+
; N/A           ; None              ; 8.190 ns        ; a    ; y  ;
; N/A           ; None              ; 8.395 ns        ; s0   ; y  ;
; N/A           ; None              ; 8.479 ns        ; s1   ; y  ;
; N/A           ; None              ; 8.676 ns        ; d    ; y  ;
; N/A           ; None              ; 9.159 ns        ; c    ; y  ;
+---------------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat May 12 16:20:27 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fuyongqi -c fuyongqi --timing_analysis_only
Info: Longest tpd from source pin s0 to destination pin y is 9.282 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA2; Fanout = 2; PIN Node = 's0'
    Info: 2: + IC(3.709 ns) + CELL(0.280 ns) = 5.076 ns; Loc. = LC_X52_Y1_N2; Fanout = 1; COMB Node = 'y~107'
    Info: 3: + IC(0.322 ns) + CELL(0.366 ns) = 5.764 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'y~108'
    Info: 4: + IC(1.114 ns) + CELL(2.404 ns) = 9.282 ns; Loc. = PIN_AA3; Fanout = 0; PIN Node = 'y'
    Info: Total cell delay = 4.137 ns ( 44.57 % )
    Info: Total interconnect delay = 5.145 ns ( 55.43 % )
Info: Shortest tpd from source pin a to destination pin y is 8.190 ns
    Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_V4; Fanout = 1; PIN Node = 'a'
    Info: 2: + IC(3.158 ns) + CELL(0.280 ns) = 4.672 ns; Loc. = LC_X52_Y1_N4; Fanout = 1; COMB Node = 'y~108'
    Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 8.190 ns; Loc. = PIN_AA3; Fanout = 0; PIN Node = 'y'
    Info: Total cell delay = 3.918 ns ( 47.84 % )
    Info: Total interconnect delay = 4.272 ns ( 52.16 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat May 12 16:20:28 2007
    Info: Elapsed time: 00:00:00