fuyongqi.vhd

一些很好的FPGA设计实例

library ieee;
use ieee.std_logic_1164.all;
entity fuyongqi is
 port( a,b,c,d,s0,s1 :in std_logic;
       y: out std_logic);
 end fuyongqi;
architecture purelogic of fuyongqi is
begin 
y <= (a and not s1 and not s0) or
     (b and not s1 and s1)or
     (c and s1 and not s0)or
     (d and s1 and s0);
end  purelogic ;