📄 yimaqi.tan.rpt
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Timing Analyzer report for YIMAQI
Tue May 15 16:58:46 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. tpd
5. Minimum tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1S10F484C5 ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.375 ns ; x[0] ; y[1] ; ; ; 0 ;
; Worst-case Minimum tpd ; N/A ; None ; 8.438 ns ; x[1] ; y[0] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.375 ns ; x[0] ; y[1] ;
; N/A ; None ; 10.291 ns ; x[4] ; y[1] ;
; N/A ; None ; 10.112 ns ; x[5] ; y[1] ;
; N/A ; None ; 10.014 ns ; x[4] ; y[0] ;
; N/A ; None ; 10.012 ns ; x[2] ; y[0] ;
; N/A ; None ; 10.001 ns ; x[0] ; y[2] ;
; N/A ; None ; 9.947 ns ; x[6] ; y[0] ;
; N/A ; None ; 9.892 ns ; x[1] ; y[1] ;
; N/A ; None ; 9.868 ns ; x[0] ; y[0] ;
; N/A ; None ; 9.710 ns ; x[1] ; y[2] ;
; N/A ; None ; 9.651 ns ; x[2] ; y[2] ;
; N/A ; None ; 9.570 ns ; x[6] ; y[1] ;
; N/A ; None ; 9.528 ns ; x[3] ; y[2] ;
; N/A ; None ; 9.501 ns ; x[4] ; y[2] ;
; N/A ; None ; 9.500 ns ; x[5] ; y[0] ;
; N/A ; None ; 9.500 ns ; x[5] ; y[2] ;
; N/A ; None ; 9.289 ns ; x[6] ; y[2] ;
; N/A ; None ; 9.230 ns ; x[7] ; y[0] ;
; N/A ; None ; 9.230 ns ; x[7] ; y[1] ;
; N/A ; None ; 9.230 ns ; x[7] ; y[2] ;
; N/A ; None ; 9.187 ns ; x[1] ; y[0] ;
; N/A ; None ; 9.126 ns ; x[2] ; y[1] ;
; N/A ; None ; 9.000 ns ; x[3] ; y[0] ;
; N/A ; None ; 9.000 ns ; x[3] ; y[1] ;
+-------+-------------------+-----------------+------+------+
+-------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+------+------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+------+
; N/A ; None ; 8.438 ns ; x[1] ; y[0] ;
; N/A ; None ; 8.572 ns ; x[2] ; y[1] ;
; N/A ; None ; 8.576 ns ; x[7] ; y[1] ;
; N/A ; None ; 8.622 ns ; x[3] ; y[2] ;
; N/A ; None ; 8.622 ns ; x[3] ; y[1] ;
; N/A ; None ; 8.622 ns ; x[3] ; y[0] ;
; N/A ; None ; 8.657 ns ; x[5] ; y[2] ;
; N/A ; None ; 8.681 ns ; x[6] ; y[2] ;
; N/A ; None ; 8.681 ns ; x[4] ; y[2] ;
; N/A ; None ; 8.750 ns ; x[2] ; y[2] ;
; N/A ; None ; 8.750 ns ; x[2] ; y[0] ;
; N/A ; None ; 8.818 ns ; x[1] ; y[2] ;
; N/A ; None ; 8.818 ns ; x[1] ; y[1] ;
; N/A ; None ; 8.870 ns ; x[7] ; y[2] ;
; N/A ; None ; 8.871 ns ; x[7] ; y[0] ;
; N/A ; None ; 9.101 ns ; x[0] ; y[2] ;
; N/A ; None ; 9.101 ns ; x[0] ; y[1] ;
; N/A ; None ; 9.101 ns ; x[0] ; y[0] ;
; N/A ; None ; 9.112 ns ; x[6] ; y[1] ;
; N/A ; None ; 9.112 ns ; x[6] ; y[0] ;
; N/A ; None ; 9.320 ns ; x[5] ; y[1] ;
; N/A ; None ; 9.320 ns ; x[5] ; y[0] ;
; N/A ; None ; 9.321 ns ; x[4] ; y[1] ;
; N/A ; None ; 9.321 ns ; x[4] ; y[0] ;
+---------------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue May 15 16:58:45 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off YIMAQI -c YIMAQI --timing_analysis_only
Info: Longest tpd from source pin x[0] to destination pin y[1] is 10.375 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_Y5; Fanout = 5; PIN Node = 'x[0]'
Info: 2: + IC(3.944 ns) + CELL(0.366 ns) = 5.397 ns; Loc. = LC_X50_Y1_N6; Fanout = 1; COMB Node = 'y~492'
Info: 3: + IC(0.488 ns) + CELL(0.075 ns) = 5.960 ns; Loc. = LC_X51_Y1_N4; Fanout = 1; COMB Node = 'y~490'
Info: 4: + IC(0.521 ns) + CELL(0.366 ns) = 6.847 ns; Loc. = LC_X50_Y1_N0; Fanout = 1; COMB Node = 'y~496'
Info: 5: + IC(1.124 ns) + CELL(2.404 ns) = 10.375 ns; Loc. = PIN_AB4; Fanout = 0; PIN Node = 'y[1]'
Info: Total cell delay = 4.298 ns ( 41.43 % )
Info: Total interconnect delay = 6.077 ns ( 58.57 % )
Info: Shortest tpd from source pin x[1] to destination pin y[0] is 8.438 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA4; Fanout = 5; PIN Node = 'x[1]'
Info: 2: + IC(3.756 ns) + CELL(0.075 ns) = 4.918 ns; Loc. = LC_X50_Y1_N3; Fanout = 1; COMB Node = 'y~506'
Info: 3: + IC(1.116 ns) + CELL(2.404 ns) = 8.438 ns; Loc. = PIN_Y2; Fanout = 0; PIN Node = 'y[0]'
Info: Total cell delay = 3.566 ns ( 42.26 % )
Info: Total interconnect delay = 4.872 ns ( 57.74 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 15 16:58:46 2007
Info: Elapsed time: 00:00:00
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