yimaqi.vhd

一些很好的FPGA设计实例

-------------只有一个输入是高电平，它将被编码后输出
----------------方案1：with when/else
library ieee;
use ieee.std_logic_1164.all;
---------------------------------
entity YIMAQI is 
port ( x:in std_logic_vector(7 downto 0);
       y: out std_logic_vector(2 downto 0));
end YIMAQI;
---------------------------------
architecture encoder1 of YIMAQI is
  begin 
 y <= "000" when x="00000001" else
      "001" when x="00000010" else
      "010" when x="00000100" else
      "011" when x="00001000" else
      "100" when x="00010000" else
      "101" when x="00100000" else
      "110" when x="01000000" else
      "111" when x="10000000" else
      "ZZZ";
END encoder1;
----------------方案二：with with/select/when
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------
entity YIMAQI is 
port ( x:in std_logic_vector(7 downto 0);
       y: out std_logic_vector(2 downto 0));
end YIMAQI;
---------------------------------
architecture encoder2 of YIMAQI is
  begin 
  with x select 
   y <= "000" when "00000001",
        "001" when "00000010",
        "010" when "00000100",
        "011" when "00001000",
        "100" when "00010000",
        "101" when "00100000",
        "110" when "01000000",
        "111" when "10000000",
        "ZZZ" when OTHERS;
  END encoder2;
---------------------
--当信号的位数增加时，列表很长，可以使用generate语句和loop语句进行描述