cudaqi.vhd

一些很好的FPGA设计实例

-----------------方案１：not_ok-----------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------
entity cudaqi is
  port( d,clk: in std_logic;
           q: buffer std_logic;
           qbar: out std_logic);
end cudaqi;
-------------------------------------------------------
architecture not_ok of cudaqi is 
  begin 
   process(clk)
  begin 
   if (clk 'event and clk ='1')then
     q<= d;
     qbar<= not q;-- 因为q的值还没有更新，所以qbar是将以前的q值取反后输出
   end if;--正确的qbar值输出会延时一个时钟周期
 end process;
end not_ok;
--------------------------------------------------------


-----------------方案２：ok--------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------
entity cudaqi is
  port( d,clk: in std_logic;
           q: buffer std_logic;
           qbar: out std_logic);
end cudaqi;
-------------------------------------------------------
architecture ok of cudaqi is 
  begin 
   process(clk)
  begin 
   if (clk 'event and clk ='1')then
     q<= d;
    end if;
end process;
     qbar<= not q;-- 放到进程以外，与进程是并发的，当q　发生变化后，qbar的值立即可以实现更新
end ok;
-------------------------------------------------