hcq.vhd

一些很好的FPGA设计实例

library ieee;
use ieee.std_logic_1164.all;
--------------------------
entity hcq  is
port (ena: in std_logic;
       input: in std_logic_vector(7 downto 0);
       output: out std_logic_vector(7 downto 0));
end hcq;
-------------------------
architecture hcq0 of hcq is
begin 
 output <= input when (ena ='0') else
       (others => 'Z');
end hcq0;