📄 cufaqi.tan.rpt
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Timing Analyzer report for CUFAQI
Sat May 12 15:19:45 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Minimum tco
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1S10F484C5 ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 2.052 ns ; d ; q~reg0 ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.539 ns ; q~reg0 ; q ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -1.942 ns ; d ; q~reg0 ; ; clk ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 6.539 ns ; q~reg0 ; q ; clk ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 2.052 ns ; d ; q~reg0 ; clk ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 6.539 ns ; q~reg0 ; q ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; -1.942 ns ; d ; q~reg0 ; clk ;
+---------------+-------------+-----------+------+--------+----------+
+------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+--------+----+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+--------+----+------------+
; N/A ; None ; 6.539 ns ; q~reg0 ; q ; clk ;
+---------------+------------------+----------------+--------+----+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Sat May 12 15:19:44 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off CUFAQI -c CUFAQI --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: No valid register-to-register paths exist for clock clk
Info: tsu for register q~reg0 (data pin = d, clock pin = clk) is 2.052 ns
Info: + Longest pin to register delay is 4.857 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J15; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(3.685 ns) + CELL(0.085 ns) = 4.857 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.172 ns ( 24.13 % )
Info: Total interconnect delay = 3.685 ns ( 75.87 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock clk to destination register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.629 ns ( 57.87 % )
Info: Total interconnect delay = 1.186 ns ( 42.13 % )
Info: tco from clock clk to destination pin q through register q~reg0 is 6.539 ns
Info: + Longest clock path from clock clk to source register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.629 ns ( 57.87 % )
Info: Total interconnect delay = 1.186 ns ( 42.13 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.568 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: 2: + IC(1.164 ns) + CELL(2.404 ns) = 3.568 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 2.404 ns ( 67.38 % )
Info: Total interconnect delay = 1.164 ns ( 32.62 % )
Info: th for register q~reg0 (data pin = d, clock pin = clk) is -1.942 ns
Info: + Longest clock path from clock clk to destination register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.629 ns ( 57.87 % )
Info: Total interconnect delay = 1.186 ns ( 42.13 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 4.857 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_J15; Fanout = 1; PIN Node = 'd'
Info: 2: + IC(3.685 ns) + CELL(0.085 ns) = 4.857 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.172 ns ( 24.13 % )
Info: Total interconnect delay = 3.685 ns ( 75.87 % )
Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.539 ns
Info: + Shortest clock path from clock clk to source register is 2.815 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F14; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.186 ns) + CELL(0.542 ns) = 2.815 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: Total cell delay = 1.629 ns ( 57.87 % )
Info: Total interconnect delay = 1.186 ns ( 42.13 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Shortest register to pin delay is 3.568 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y30_N2; Fanout = 1; REG Node = 'q~reg0'
Info: 2: + IC(1.164 ns) + CELL(2.404 ns) = 3.568 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'q'
Info: Total cell delay = 2.404 ns ( 67.38 % )
Info: Total interconnect delay = 1.164 ns ( 32.62 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sat May 12 15:19:45 2007
Info: Elapsed time: 00:00:01
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