cufaqi.fit.rpt

一些很好的FPGA设计实例

+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Auto-restart configuration after error       ; On                       ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve Data[0] pin after configuration      ; As input tri-stated      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.fit.eqn.


+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in d:/vhdl数字逻辑教程/2.1带有异步复位端的d触发器/CUFAQI.pin.


+-------------------------------------------------------+
; Fitter Resource Usage Summary                         ;
+--------------------------------+----------------------+
; Resource                       ; Usage                ;
+--------------------------------+----------------------+
; Logic cells                    ; 1 / 10,570 ( < 1 % ) ;
; Registers                      ; 1 / 12,506 ( < 1 % ) ;
; Total LABs                     ; 1 / 1,057 ( < 1 % )  ;
; Logic elements in carry chains ; 0                    ;
; User inserted logic cells      ; 0                    ;
; Virtual pins                   ; 0                    ;
; I/O pins                       ; 4 / 336 ( 1 % )      ;
;     -- Clock pins              ; 0 / 16 ( 0 % )       ;
; Global signals                 ; 0                    ;
; M512s                          ; 0 / 94 ( 0 % )       ;
; M4Ks                           ; 0 / 60 ( 0 % )       ;
; M-RAMs                         ; 0 / 1 ( 0 % )        ;
; Total memory bits              ; 0 / 920,448 ( 0 % )  ;
; Total RAM block bits           ; 0 / 920,448 ( 0 % )  ;
; DSP block 9-bit elements       ; 0 / 48 ( 0 % )       ;
; Global clocks                  ; 0 / 16 ( 0 % )       ;
; Regional clocks                ; 0 / 16 ( 0 % )       ;
; Fast regional clocks           ; 0 / 8 ( 0 % )        ;
; DIFFIOCLKs                     ; 0 / 16 ( 0 % )       ;
; SERDES transmitters            ; 0 / 44 ( 0 % )       ;
; SERDES receivers               ; 0 / 44 ( 0 % )       ;
; Maximum fan-out node           ; q~reg0               ;
; Maximum fan-out                ; 1                    ;
; Total fan-out                  ; 4                    ;
; Average fan-out                ; 0.67                 ;
+--------------------------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                 ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk  ; F14   ; 3        ; 17           ; 31           ; 3           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
; d    ; J15   ; 3        ; 17           ; 31           ; 5           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
; rst  ; D14   ; 3        ; 17           ; 31           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; Fitter               ;
+------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                     ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; q    ; L16   ; 3        ; 17           ; 31           ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; Fitter               ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 0 / 29 ( 0 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 30 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 4 / 51 ( 7 % ) ; 3.3V          ; --           ;
; 4        ; 1 / 52 ( 1 % ) ; 3.3V          ; --           ;
; 5        ; 0 / 29 ( 0 % ) ; 3.3V          ; --           ;
; 6        ; 0 / 29 ( 0 % ) ; 3.3V          ; --           ;
; 7        ; 0 / 52 ( 0 % ) ; 3.3V          ; --           ;
; 8        ; 0 / 51 ( 0 % ) ; 3.3V          ; --           ;
; 9        ; 0 / 6 ( 0 % )  ; 3.3V          ; --           ;
; 11       ; 0 / 6 ( 0 % )  ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                            ;
+----------+------------+----------+---------------------------+--------+--------------+---------+------------+-------------+-----------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage            ; Dir.   ; I/O Standard ; Voltage ; I/O Type   ; Termination ; User Assignment ;
+----------+------------+----------+---------------------------+--------+--------------+---------+------------+-------------+-----------------+
; A1       ;            ;          ; VCCINT                    ; power  ;              ; 1.5V    ; --         ; --          ;                 ;
; A2       ;            ; 1        ; GND                       ; gnd    ;              ;         ; --         ; --          ;                 ;