cufaqi.vhd

一些很好的FPGA设计实例

library ieee;
use ieee.std_logic_1164.all;
entity CUFAQI is
   port(d, clk, rst: in std_logic;
        q: out std_logic);
end CUFAQI;
architecture behavior of CUFAQI is
begin 
  process(rst,clk)
  begin 
    if(rst= '1') then
    q <= '0';
   ELSIF (clk 'EVENT and clk='1')then
    q <= d;
    end if;
  end process;
end behavior;