bijiaoqi.hier_info

一些很好的FPGA设计实例

|bijiaoqi
a[0] => LessThan~0.IN8
a[0] => equal~0.IN0
a[0] => LessThan~1.IN8
a[1] => LessThan~0.IN7
a[1] => equal~1.IN0
a[1] => LessThan~1.IN7
a[2] => LessThan~0.IN6
a[2] => equal~2.IN0
a[2] => LessThan~1.IN6
a[3] => LessThan~0.IN5
a[3] => equal~3.IN0
a[3] => LessThan~1.IN5
a[4] => LessThan~0.IN4
a[4] => equal~4.IN0
a[4] => LessThan~1.IN4
a[5] => LessThan~0.IN3
a[5] => equal~5.IN0
a[5] => LessThan~1.IN3
a[6] => LessThan~0.IN2
a[6] => equal~6.IN0
a[6] => LessThan~1.IN2
a[7] => LessThan~0.IN1
a[7] => equal~7.IN0
a[7] => LessThan~1.IN1
b[0] => LessThan~0.IN16
b[0] => equal~0.IN1
b[0] => LessThan~1.IN16
b[1] => LessThan~0.IN15
b[1] => equal~1.IN1
b[1] => LessThan~1.IN15
b[2] => LessThan~0.IN14
b[2] => equal~2.IN1
b[2] => LessThan~1.IN14
b[3] => LessThan~0.IN13
b[3] => equal~3.IN1
b[3] => LessThan~1.IN13
b[4] => LessThan~0.IN12
b[4] => equal~4.IN1
b[4] => LessThan~1.IN12
b[5] => LessThan~0.IN11
b[5] => equal~5.IN1
b[5] => LessThan~1.IN11
b[6] => LessThan~0.IN10
b[6] => equal~6.IN1
b[6] => LessThan~1.IN10
b[7] => LessThan~0.IN9
b[7] => equal~7.IN1
b[7] => LessThan~1.IN9
x1 <= LessThan~0.DB_MAX_OUTPUT_PORT_TYPE
x2 <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE
x3 <= LessThan~1.DB_MAX_OUTPUT_PORT_TYPE