bijiaoqi.tan.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 14:42:47 2007 " "Info: Processing started: Thu May 17 14:42:47 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off bijiaoqi -c bijiaoqi --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off bijiaoqi -c bijiaoqi --timing_analysis_only" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[7\] x2 10.148 ns Longest " "Info: Longest tpd from source pin b\[7\] to destination pin x2 is 10.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns b\[7\] 1 PIN PIN_G5 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G5; Fanout = 3; PIN Node = 'b\[7\]'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "" { b[7] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.872 ns) + CELL(0.366 ns) 5.472 ns reduce_nor~38 2 COMB LC_X52_Y30_N8 1 " "Info: 2: + IC(3.872 ns) + CELL(0.366 ns) = 5.472 ns; Loc. = LC_X52_Y30_N8; Fanout = 1; COMB Node = 'reduce_nor~38'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "4.238 ns" { b[7] reduce_nor~38 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.969 ns) + CELL(0.183 ns) 6.624 ns reduce_nor~42 3 COMB LC_X52_Y28_N8 1 " "Info: 3: + IC(0.969 ns) + CELL(0.183 ns) = 6.624 ns; Loc. = LC_X52_Y28_N8; Fanout = 1; COMB Node = 'reduce_nor~42'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "1.152 ns" { reduce_nor~38 reduce_nor~42 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.148 ns) + CELL(2.376 ns) 10.148 ns x2 4 PIN PIN_G3 0 " "Info: 4: + IC(1.148 ns) + CELL(2.376 ns) = 10.148 ns; Loc. = PIN_G3; Fanout = 0; PIN Node = 'x2'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "3.524 ns" { reduce_nor~42 x2 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.159 ns 40.98 % " "Info: Total cell delay = 4.159 ns ( 40.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.989 ns 59.02 % " "Info: Total interconnect delay = 5.989 ns ( 59.02 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "10.148 ns" { b[7] reduce_nor~38 reduce_nor~42 x2 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[7\] x3 8.068 ns Shortest " "Info: Shortest tpd from source pin b\[7\] to destination pin x3 is 8.068 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns b\[7\] 1 PIN PIN_G5 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_G5; Fanout = 3; PIN Node = 'b\[7\]'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "" { b[7] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.632 ns) + CELL(0.075 ns) 4.941 ns LessThan~17 2 COMB LC_X52_Y29_N7 1 " "Info: 2: + IC(3.632 ns) + CELL(0.075 ns) = 4.941 ns; Loc. = LC_X52_Y29_N7; Fanout = 1; COMB Node = 'LessThan~17'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "3.707 ns" { b[7] LessThan~17 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(2.376 ns) 8.068 ns x3 3 PIN PIN_F5 0 " "Info: 3: + IC(0.751 ns) + CELL(2.376 ns) = 8.068 ns; Loc. = PIN_F5; Fanout = 0; PIN Node = 'x3'" {  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "3.127 ns" { LessThan~17 x3 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/bijiaoqi.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.685 ns 45.67 % " "Info: Total cell delay = 3.685 ns ( 45.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.383 ns 54.33 % " "Info: Total interconnect delay = 4.383 ns ( 54.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi_cmp.qrpt" Compiler "bijiaoqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/典型电路设计分析/9.2有符号数比较器和无符号数比较器/db/bijiaoqi.quartus_db" { Floorplan "" "" "8.068 ns" { b[7] LessThan~17 x3 } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 14:42:49 2007 " "Info: Processing ended: Thu May 17 14:42:49 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}