有限状态机设计风格模板#1.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 49 行

---------------------------有限状态机设计风格模板#1
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity <entity_name> is
   port(input: in<data_type>;
        reset,clock：in std_logic;
         output: out<data_state>);
end <entity_name>;
-------------------------------
architecture <arch_name> of <entity_name> is
   type state is (state0,state1,state2,state3,...);
   signal pr_state,nx_state: state;
begin
--------------------lower section------------------
process (reset,colock)
begin
  if(reset = '1')then
     pr_state <= state0;
  elsif (clock 'event and clock = '1')then
  pr_state <= nx_state;
  end if;
end process;
-----------------------upper section----------------
process (input, pr_state)
begin
  case pr_state is
  when state0 =>
    if(input=...)then
       output <= <value>;
       nx_state <= state1;
    else...
    end if;
  when state1 =>
    if(input=...)then
       output <= <value>;
       nx_state <= state2;
    else...
    end if;
  when state2 =>
    if(input=...)then
       output <= <value>;
       nx_state <= state3;
    else...
    end if;
............
  end case;;
end process;
end <arch_name>;