fuyongqi.vhd

一些很好的FPGA设计实例

----------方案一：with when/else
library ieee;
use ieee.std_logic_1164.all;
entity fuyongqi is
port( a,b,c,d:in std_logic;
     sel :in std_logic_vector(1 downto 0);
      y: out std_logic);
end fuyongqi;
architecture fuyongqi1 of fuyongqi is
begin 
y <= a when sel="00" else
     b when sel="01" else
     c when sel="01" else
     d ;
end fuyongqi1;
--------------------------------
--------方案二：with with/select/when
library ieee;
use ieee.std_logic_1164.all;
entity fuyongqi is
port( a,b,c,d:in std_logic;
     sel :in std_logic_vector(1 downto 0);
      y: out std_logic);
end fuyongqi;
-----------------------------
architecture fuyongqi2 of fuyongqi is
begin 
with sel select
   y<= a when "00",--注意使用的是,不是;
       b when "01",
       c when "10",
       d when others;---不能是d when "11"；
end fuyongqi2;
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-------sel信号也可以声明为integer类型
-----------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------
entity fuyongqi is
port( a,b,c,d:in std_logic;
     sel :in integer range 0 to 3;
      y: out std_logic);
end fuyongqi;
----------------方案一：with when/else
architecture fuyongqi1 of fuyongqi is
begin 
y <= a when sel= 0 else
     b when sel= 1 else
     c when sel= 2 else
     d ;
end fuyongqi1;
-----------------方案二：with with/select/when
architecture fuyongqi2 of fuyongqi is
begin 
with sel select
   y<= a when 0,--注意使用的是,不是;
       b when 1,
       c when 2,
       d when 3;---这里用'3'和others是等效的
end fuyongqi2;----sel的所有情况都应该考虑
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