fenpinqi.map.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 16 15:50:53 2007 " "Info: Processing started: Wed May 16 15:50:53 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off fenpinqi -c fenpinqi " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fenpinqi -c fenpinqi" {  } {  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "? fenpinqi.vhd(8) " "Error: VHDL syntax error at fenpinqi.vhd(8) near text ?" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 8 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"? fenpinqi.vhd(8) " "Error: VHDL syntax error at fenpinqi.vhd(8) near text \"?" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 8 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "fenpinqi fenpinqi.vhd(7) " "Error: Ignored construct fenpinqi at fenpinqi.vhd(7) because of previous errors" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 7 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_UNCOMPILED_ENTITY" "fenpinqi fenpinqi.vhd(12) " "Error: VHDL error at fenpinqi.vhd(12): entity fenpinqi is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 12 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "integer fenpinqi.vhd(13) " "Error: VHDL error at fenpinqi.vhd(13): object integer is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 13 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "integer fenpinqi.vhd(16) " "Error: VHDL error at fenpinqi.vhd(16): object integer is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 16 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "count1 fenpinqi.vhd(19) " "Error: VHDL error at fenpinqi.vhd(19): object count1 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 19 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "count2 fenpinqi.vhd(20) " "Error: VHDL error at fenpinqi.vhd(20): object count2 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 20 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"count1\"; expecting \";\" fenpinqi.vhd(23) " "Error: VHDL syntax error at fenpinqi.vhd(23) near text \"count1\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "out1 fenpinqi.vhd(22) " "Error: VHDL error at fenpinqi.vhd(22): object out1 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 22 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "count1 fenpinqi.vhd(21) " "Error: VHDL error at fenpinqi.vhd(21): object count1 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"count2\"; expecting \";\" fenpinqi.vhd(27) " "Error: VHDL syntax error at fenpinqi.vhd(27) near text \"count2\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 27 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "out1 fenpinqi.vhd(26) " "Error: VHDL error at fenpinqi.vhd(26): object out1 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 26 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "count2 fenpinqi.vhd(25) " "Error: VHDL error at fenpinqi.vhd(25): object count2 is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 25 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "clk fenpinqi.vhd(18) " "Error: VHDL error at fenpinqi.vhd(18): object clk is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 18 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "clk fenpinqi.vhd(15) " "Error: VHDL error at fenpinqi.vhd(15): object clk is used but not declared" {  } { { "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.5分频器/fenpinqi.vhd" 15 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpinqi.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file fenpinqi.vhd" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 16 s 0 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 16 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed May 16 15:50:55 2007 " "Error: Processing ended: Wed May 16 15:50:55 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}