fenpinqi.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 32 行

--对时钟进行６分频的电路：两个输出，一个基于信号count1一个基于变量count2

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library ieee;
use ieee.std_logic_1164.all;
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entity fenpinqi is
　port ( clk : in std_logic;
       out1,out2 : buffer std_logic);
end fenpinqi;
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architecture example of fenpinqi is
   signal count1: integer range 0 to 7;
begin 
   process(clk)
   variable count2 : integer range 0 to 7;
begin 
  if (clk 'event and clk = '1')then
  count1 <=count1+1;
  count2 <=count2+1;
      if (count1 = 5 )then
      out1 <= not out1
      count1 <= 0;
      end if;
      if (count2 = 5 )then
      out1 <= not out2
      count2 := 0;
      end if;
  end if;
   end process;
end example;
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