cufaqi.vhd

一些很好的FPGA设计实例

--当一个信号的赋值是以另一个信号的跳变为条件时，或者说当发生同步赋值时编译会产生寄存器
--如果变量的值没有被进程（函数或过程）以外的代码调用，那么不一定会产生寄存器
---如果一个变量是在一个信号跳变时被赋值的，并且该值又被赋给了另外的信号，那么综合后
---生成寄存器
---如果一个变量在还没有进行赋值操作时已被使用，那么在综合后就会产生寄存器
------------------------------------------------------------------------------------
----process (clk)
----begin 
  -----if (clk 'event and clk ='1')then 
-----output1 <= temp;---output1被存储因为是在另一个信号跳变时被赋值的
----output2 <= a;---output2 被存储因为是在另一个信号跳变时被赋值的
----end if;
----end process;
------------------------------------------------------------------
----process (clk)
----begin 
 ---- if (clk 'event and clk ='1')then 
----output1 <= temp;---output1被存储
----end if;
----output2 <= a;---output2 未被存储
----end process;
------------------------------------------------------------------
----process (clk)
----variable temp : bit;
----begin 
----  if (clk 'event and clk ='1')then 
----    temp <= a;
----end if;
 ----   x <= temp;   --temp 促使x被存储
----end process;
------------------------------------------------------------------
-----------------方案１：two dffs-----------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------
entity cufaqi is
  port( d,clk: in std_logic;
           q: buffer std_logic;
           qbar: out std_logic);
end cufaqi;
-------------------------------------------------------
architecture two_dffs of cufaqi is 
  begin 
   process(clk)
  begin 
   if (clk 'event and clk ='1')then
     q<= d;--generate a register
     qbar<= not d;--generate a register
   end if;
 end process;
end two_dffs;
--------------------------------------------------------


-----------------方案２：one dff--------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------
entity cudaqi is
  port( d,clk: in std_logic;
           q: buffer std_logic;
           qbar: out std_logic);
end cufaqi;
-------------------------------------------------------
architecture ok of cufaqi is 
  begin 
   process(clk)
  begin 
   if (clk 'event and clk ='1')then
     q<= d;--generate a register
    end if;
end process;
     qbar<= not q;--use logic gate(no register)
end one_dff;
-------------------------------------------------
--方案１有两个同步的信号赋值，所以有两个触发器