📄 yimaqi.tan.rpt
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Timing Analyzer report for yimaqi
Mon May 14 17:04:16 2007
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. tpd
5. Minimum tpd
6. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1S10F484C5 ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+---------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.021 ns ; sel[1] ; x[1] ; ; ; 0 ;
; Worst-case Minimum tpd ; N/A ; None ; 8.483 ns ; sel[2] ; x[5] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+------+------------+----------+--------------+
+-------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+--------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+--------+------+
; N/A ; None ; 9.021 ns ; sel[1] ; x[1] ;
; N/A ; None ; 9.009 ns ; sel[1] ; x[0] ;
; N/A ; None ; 9.007 ns ; sel[1] ; x[4] ;
; N/A ; None ; 8.997 ns ; sel[1] ; x[7] ;
; N/A ; None ; 8.986 ns ; sel[1] ; x[2] ;
; N/A ; None ; 8.985 ns ; sel[1] ; x[6] ;
; N/A ; None ; 8.915 ns ; sel[0] ; x[1] ;
; N/A ; None ; 8.904 ns ; sel[0] ; x[0] ;
; N/A ; None ; 8.902 ns ; sel[0] ; x[4] ;
; N/A ; None ; 8.891 ns ; sel[0] ; x[7] ;
; N/A ; None ; 8.881 ns ; sel[0] ; x[2] ;
; N/A ; None ; 8.880 ns ; sel[0] ; x[6] ;
; N/A ; None ; 8.809 ns ; ena ; x[1] ;
; N/A ; None ; 8.797 ns ; ena ; x[0] ;
; N/A ; None ; 8.795 ns ; ena ; x[4] ;
; N/A ; None ; 8.794 ns ; sel[1] ; x[5] ;
; N/A ; None ; 8.785 ns ; ena ; x[7] ;
; N/A ; None ; 8.782 ns ; sel[1] ; x[3] ;
; N/A ; None ; 8.773 ns ; ena ; x[2] ;
; N/A ; None ; 8.773 ns ; ena ; x[6] ;
; N/A ; None ; 8.709 ns ; sel[2] ; x[1] ;
; N/A ; None ; 8.698 ns ; sel[2] ; x[0] ;
; N/A ; None ; 8.698 ns ; sel[2] ; x[4] ;
; N/A ; None ; 8.696 ns ; sel[2] ; x[7] ;
; N/A ; None ; 8.689 ns ; sel[0] ; x[5] ;
; N/A ; None ; 8.681 ns ; sel[2] ; x[2] ;
; N/A ; None ; 8.677 ns ; sel[0] ; x[3] ;
; N/A ; None ; 8.674 ns ; sel[2] ; x[6] ;
; N/A ; None ; 8.581 ns ; ena ; x[5] ;
; N/A ; None ; 8.570 ns ; ena ; x[3] ;
; N/A ; None ; 8.484 ns ; sel[2] ; x[3] ;
; N/A ; None ; 8.483 ns ; sel[2] ; x[5] ;
+-------+-------------------+-----------------+--------+------+
+---------------------------------------------------------------------+
; Minimum tpd ;
+---------------+-------------------+-----------------+--------+------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+--------+------+
; N/A ; None ; 8.483 ns ; sel[2] ; x[5] ;
; N/A ; None ; 8.484 ns ; sel[2] ; x[3] ;
; N/A ; None ; 8.570 ns ; ena ; x[3] ;
; N/A ; None ; 8.581 ns ; ena ; x[5] ;
; N/A ; None ; 8.674 ns ; sel[2] ; x[6] ;
; N/A ; None ; 8.677 ns ; sel[0] ; x[3] ;
; N/A ; None ; 8.681 ns ; sel[2] ; x[2] ;
; N/A ; None ; 8.689 ns ; sel[0] ; x[5] ;
; N/A ; None ; 8.696 ns ; sel[2] ; x[7] ;
; N/A ; None ; 8.698 ns ; sel[2] ; x[4] ;
; N/A ; None ; 8.698 ns ; sel[2] ; x[0] ;
; N/A ; None ; 8.709 ns ; sel[2] ; x[1] ;
; N/A ; None ; 8.773 ns ; ena ; x[6] ;
; N/A ; None ; 8.773 ns ; ena ; x[2] ;
; N/A ; None ; 8.782 ns ; sel[1] ; x[3] ;
; N/A ; None ; 8.785 ns ; ena ; x[7] ;
; N/A ; None ; 8.794 ns ; sel[1] ; x[5] ;
; N/A ; None ; 8.795 ns ; ena ; x[4] ;
; N/A ; None ; 8.797 ns ; ena ; x[0] ;
; N/A ; None ; 8.809 ns ; ena ; x[1] ;
; N/A ; None ; 8.880 ns ; sel[0] ; x[6] ;
; N/A ; None ; 8.881 ns ; sel[0] ; x[2] ;
; N/A ; None ; 8.891 ns ; sel[0] ; x[7] ;
; N/A ; None ; 8.902 ns ; sel[0] ; x[4] ;
; N/A ; None ; 8.904 ns ; sel[0] ; x[0] ;
; N/A ; None ; 8.915 ns ; sel[0] ; x[1] ;
; N/A ; None ; 8.985 ns ; sel[1] ; x[6] ;
; N/A ; None ; 8.986 ns ; sel[1] ; x[2] ;
; N/A ; None ; 8.997 ns ; sel[1] ; x[7] ;
; N/A ; None ; 9.007 ns ; sel[1] ; x[4] ;
; N/A ; None ; 9.009 ns ; sel[1] ; x[0] ;
; N/A ; None ; 9.021 ns ; sel[1] ; x[1] ;
+---------------+-------------------+-----------------+--------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Mon May 14 17:04:15 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off yimaqi -c yimaqi --timing_analysis_only
Info: Longest tpd from source pin sel[1] to destination pin x[1] is 9.021 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB17; Fanout = 8; PIN Node = 'sel[1]'
Info: 2: + IC(3.823 ns) + CELL(0.366 ns) = 5.276 ns; Loc. = LC_X5_Y1_N5; Fanout = 1; COMB Node = 'temp1~14'
Info: 3: + IC(1.341 ns) + CELL(2.404 ns) = 9.021 ns; Loc. = PIN_Y19; Fanout = 0; PIN Node = 'x[1]'
Info: Total cell delay = 3.857 ns ( 42.76 % )
Info: Total interconnect delay = 5.164 ns ( 57.24 % )
Info: Shortest tpd from source pin sel[2] to destination pin x[5] is 8.483 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_W17; Fanout = 8; PIN Node = 'sel[2]'
Info: 2: + IC(3.801 ns) + CELL(0.075 ns) = 4.963 ns; Loc. = LC_X5_Y1_N7; Fanout = 1; COMB Node = 'temp1~10'
Info: 3: + IC(1.116 ns) + CELL(2.404 ns) = 8.483 ns; Loc. = PIN_V18; Fanout = 0; PIN Node = 'x[5]'
Info: Total cell delay = 3.566 ns ( 42.04 % )
Info: Total interconnect delay = 4.917 ns ( 57.96 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Mon May 14 17:04:16 2007
Info: Elapsed time: 00:00:00
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