yimaqi.fit.qmsg

一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 14 17:02:42 2007 " "Info: Processing started: Mon May 14 17:02:42 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off yimaqi -c yimaqi " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off yimaqi -c yimaqi" {  } {  } 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "yimaqi EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design yimaqi" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F484C5 " "Info: Device EP1S20F484C5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "12 12 " "Info: No exact pin location assignment(s) for 12 pins of 12 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[7\] " "Info: Pin x\[7\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[7\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[7] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[6\] " "Info: Pin x\[6\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[6\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[6] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[5\] " "Info: Pin x\[5\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[5\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[5] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[4\] " "Info: Pin x\[4\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[4\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[4] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[3\] " "Info: Pin x\[3\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[3\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[3] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[2\] " "Info: Pin x\[2\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[2\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[2] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[1\] " "Info: Pin x\[1\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[1\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "x\[0\] " "Info: Pin x\[0\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 10 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "x\[0\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { x[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { x[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "ena " "Info: Pin ena not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 8 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "ena" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { ena } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { ena } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[0\] " "Info: Pin sel\[0\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 9 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sel\[0\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { sel[0] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { sel[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[1\] " "Info: Pin sel\[1\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 9 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sel\[1\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { sel[1] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { sel[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "sel\[2\] " "Info: Pin sel\[2\] not assigned to an exact location on the device" {  } { { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.vhd" 9 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "sel\[2\]" } } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi_cmp.qrpt" Compiler "yimaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/4.1通用译码器/db/yimaqi.quartus_db" { Floorplan "" "" "" { sel[2] } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { Floorplan "d:/vhdl数字逻辑教程/4.1通用译码器/yimaqi.fld" "" "" { sel[2] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}