example.vhd

来自「一些很好的FPGA设计实例」· VHDL 代码 · 共 15 行

entity example is
    port ( a, b, clk : in bit;
          q : out bit );
end example;
 architecture examp of example is
 signal temp : bit;
begin 
 temp <= a nand b;
process (clk)
begin 
     if (clk 'event and clk= '1') then q <= temp;
     end if;
end process;
end examp;